O Consumo de Energia da Arquitetura DTSVLIW
Resumo
Neste trabalho apresentamos um estudo sobre o consumo de energia da arquitetura DTSVLIW. Nós implementamos uma versão do nosso simulador DTSVLIW capaz de medir tanto o consumo de energia dinâmico quanto o estático. Comparamos estes resultados com os de simuladores da arquitetura do processador Alpha 21264, como o Wattch e o Hotleackage. Os experimentos mostraram que a arquitetura DTSVLIW consome consideravelmente menos energia que o processador Alpha 21264.
Referências
P. Avouris, "Supertubes", IEEE Spectrum, Vol. 41, No. 8 (INT), p. 34-39, August 2004.
Digital Equipment Corporation, "Alpha Architecture Handbook", Digital Equipment Corporation, 1992.
D. W. Bailey, B. J. Benschneider, "Clocking Design and Analysis for a 600MHz Alpha Microprocessor", IEEE Journal of Solid-State Circuits, Vol. 33, No. 11, pp. 1627-1633, Nov. 1998.
D. Brooks, V. Tiwari, and M. Martonosi, "Wattch: A framework for architectural-level power analysis and optimizations", Proceedings of the 27th Annual International Symposium on Computer Architecture, pp. 83-94, June 2000.
D. Burger and J. Goodman, "Billion-transistor Architectures", IEEE Computer, Vol. 30 No. 9, pp. 46-49, Sept. 1997.
A. F. De Souza and P. Rounce, "Dynamically Trace Scheduled VLIW Architectures", Proceedings of the High-Performance Computing and Networking' 98 - HPCN'98, on Lecture Notes in Cornputer Science, Vol. 1401, pp. 993-995, Apr. 1998.
A. F. De Souza and P. Rounce, "Dynamically Scheduling VLIW Instructions", Journal of Parallel and Distributed Computing, Vol. 60, No. 12, pp. 1480-1511, Dec. 2000.
M. K. Gowan, L. L. Biro, and D. B. Jackson, "Power considerations in the design of the Alpha 21264 microprocessor", Proceedings of the 35th Design Automation Conference, pp. 726-73 1, 1998.
M. B. Kamble and K. Ghose, "Analytical Energy Dissipation Models for Low Power Caches", Proceedings of the International Syrnposium on Low-power Eletronics and Design, pp.343-348, 1997.
N. S. Kim, T. Austin, D. Blaauw, T. Mudge, K. Flautner, J. S. Hu, M. J. Irwin, M. Kandemir and V. Narayanan, "Leakage Current: Moore's Law Meets Static Power", IEEE Computer, Vol. 36, No. 12, pp. 68-75, December 2003.
A. J. Kleinüsowski and D. J. Lilja, "MinneSPEC: A New SPEC Benchmark Workload for Simulation-Based Computer Architecture Research", Computer Architecture Letters, Volume 1, June, 2002.
S. Palacharla, N. Jouppi, and J. Smith, "Complexity-Effective Superscalar Processors", Proceedings of the 24th Annual International Symposium on Computer Architecture, 1997.
S. Palacharla, N. Jouppi, and J. Smith. Quantifying the Complexity of Superscalar Processors. University of Wisconsin Computer Science Tech. Report 1328, 1997.
Semiconductor lndustry Associa tio o (SAI), "International Technology Roadmap for Semiconductors", http://public.itrs.net.
T. Wada, S. Rajan, and S. A. Przybylski, "An Analytical Access Time Model for On-Chip Cache Memories", IEEE Journal of Solid-State Cicuits, Vol.27, No.8,pp.1147-1156, Aug. 1992.
S. Wilton and N. Jouppi, "An Enhanced Access and Cycle Time Model for OnChip Caches", Technical Report No. 93/5, DEC-Western Research Lab, 1994.
Y. Zhang, D. Parikh, K. Sankaranarayanan, K. Skadron, and M. Stan, "Hotleakage: A temperature-aware model of subthreshold and gate leakage for architects", Technical Report CS-2003-05, University of Virgínia Department of Computer Science, Mar. 2003.
R. Zimmermann and W. Fichtner, "Low-power logic styles: CMOS versus pass-transistor logic", IEEE Journal of Solid-State Circuits, Vol. 32, No. 7, pp. 1079-1090, Jul. 1997.
Digital Equipment Corporation, "Alpha Architecture Handbook", Digital Equipment Corporation, 1992.
D. W. Bailey, B. J. Benschneider, "Clocking Design and Analysis for a 600MHz Alpha Microprocessor", IEEE Journal of Solid-State Circuits, Vol. 33, No. 11, pp. 1627-1633, Nov. 1998.
D. Brooks, V. Tiwari, and M. Martonosi, "Wattch: A framework for architectural-level power analysis and optimizations", Proceedings of the 27th Annual International Symposium on Computer Architecture, pp. 83-94, June 2000.
D. Burger and J. Goodman, "Billion-transistor Architectures", IEEE Computer, Vol. 30 No. 9, pp. 46-49, Sept. 1997.
A. F. De Souza and P. Rounce, "Dynamically Trace Scheduled VLIW Architectures", Proceedings of the High-Performance Computing and Networking' 98 - HPCN'98, on Lecture Notes in Cornputer Science, Vol. 1401, pp. 993-995, Apr. 1998.
A. F. De Souza and P. Rounce, "Dynamically Scheduling VLIW Instructions", Journal of Parallel and Distributed Computing, Vol. 60, No. 12, pp. 1480-1511, Dec. 2000.
M. K. Gowan, L. L. Biro, and D. B. Jackson, "Power considerations in the design of the Alpha 21264 microprocessor", Proceedings of the 35th Design Automation Conference, pp. 726-73 1, 1998.
M. B. Kamble and K. Ghose, "Analytical Energy Dissipation Models for Low Power Caches", Proceedings of the International Syrnposium on Low-power Eletronics and Design, pp.343-348, 1997.
N. S. Kim, T. Austin, D. Blaauw, T. Mudge, K. Flautner, J. S. Hu, M. J. Irwin, M. Kandemir and V. Narayanan, "Leakage Current: Moore's Law Meets Static Power", IEEE Computer, Vol. 36, No. 12, pp. 68-75, December 2003.
A. J. Kleinüsowski and D. J. Lilja, "MinneSPEC: A New SPEC Benchmark Workload for Simulation-Based Computer Architecture Research", Computer Architecture Letters, Volume 1, June, 2002.
S. Palacharla, N. Jouppi, and J. Smith, "Complexity-Effective Superscalar Processors", Proceedings of the 24th Annual International Symposium on Computer Architecture, 1997.
S. Palacharla, N. Jouppi, and J. Smith. Quantifying the Complexity of Superscalar Processors. University of Wisconsin Computer Science Tech. Report 1328, 1997.
Semiconductor lndustry Associa tio o (SAI), "International Technology Roadmap for Semiconductors", http://public.itrs.net.
T. Wada, S. Rajan, and S. A. Przybylski, "An Analytical Access Time Model for On-Chip Cache Memories", IEEE Journal of Solid-State Cicuits, Vol.27, No.8,pp.1147-1156, Aug. 1992.
S. Wilton and N. Jouppi, "An Enhanced Access and Cycle Time Model for OnChip Caches", Technical Report No. 93/5, DEC-Western Research Lab, 1994.
Y. Zhang, D. Parikh, K. Sankaranarayanan, K. Skadron, and M. Stan, "Hotleakage: A temperature-aware model of subthreshold and gate leakage for architects", Technical Report CS-2003-05, University of Virgínia Department of Computer Science, Mar. 2003.
R. Zimmermann and W. Fichtner, "Low-power logic styles: CMOS versus pass-transistor logic", IEEE Journal of Solid-State Circuits, Vol. 32, No. 7, pp. 1079-1090, Jul. 1997.
Publicado
27/10/2004
Como Citar
PEDRONI, Felipe Thomaz; ALMEIDA, Fernando Líbio L.; SOUZA, Alberto F. De.
O Consumo de Energia da Arquitetura DTSVLIW. In: SIMPÓSIO EM SISTEMAS COMPUTACIONAIS DE ALTO DESEMPENHO (SSCAD), 5. , 2004, Foz do Iguaçu.
Anais [...].
Porto Alegre: Sociedade Brasileira de Computação,
2004
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p. 82-89.
DOI: https://doi.org/10.5753/wscad.2004.19004.
