R2NP: Processador de Rede RISC Reconfigurável
Resumo
Este artigo apresenta o projeto do R2NP (Reconfigurable RISC Network Processor). Sua principal aplicação é como elemento de processamento em sistemas de comunicação de dados, efetivando e estabelecendo conexões e a comunicação entre os equipamentos e dispositivos de rede. As principais características deste processador são a reconfigurabilidade de alguns blocos lógicos, o suporte a multi-protocolo e a topologias dinâmicas, objetivando principalmente a não dependência e a então, flexibilidade de funcionamento. Para isto, o R2NP possui um conjunto de instruções específicas e microarquitetura dedicada para suportar as características mencionadas.
Referências
ADC, Cuda Packet Telephony Module (PTM) Hardware Architecture, http://www.adc.com.
Agere System, Fast Pattern Processor (FPP) Product Brief, April 2001, http://www.agere.com.
Buya, R., High Perfonnance Cluster Cornputing, Volume 1, Prentice Hall, 1999.
Cisco 7200 Series Network Processor Family, NPE-400, NPE-300 and NPE-225, Datasheet, 2000, http://www.cisco.com.
Cisco Systems White Paper, "The Evolution of high-end Router Architectures-Basic Scalability and Performance Considerations for Evaluating Large-Scale Router Designs", 2001, http://www.cisco.com.
Cisco, Route Switch Processor 8 for Cisco 7500 Series Routers, Datasheet, 2000, http://www.cisco.com.
C-Port, C5e Network Processor Product Brief, January 2002, http://www.motorola.com.
C. Ulmer, C. Wood, S. Yalamanchili, "Active SANs: Hardware Support for Integrating Computation and Communication", Workshop on Novel Uses of System Arca Networks at HPCA (SAN 2002), February 2002.
D. L. Tennenhouse, J. M. Smith, W. D. Sincoskie, O. J. Wetherall, G. J. Minden, "A Survey of Active Network Research", IEEE Communications Magazine, Volume 35, N2 I, pp.80-86, 1997.
EZChip Network Processors, http://www.ezchip.com.
H. C. Freitas, C. A. P. S. Martins, "Processador de Rede com Suporte a Multi-protocolo e Topologias Dinâmicas", II Workshop de Sistemas Computacionais de Alto Desempenho, WSCAD'2001, Pirenópolis-GO, pp.31-38.
H. C. Freitas, C. A. P. S. Martins, "Projeto de Processador com Microarquitetura Dedicada para Roteamento em Sistemas de Comunicação de Dados", I Workshop de Sistemas Computacionais de Alto Desempenho, WSCAD'2000, São Pedro-SP, pp.63, (Iniciação Científica).
H. C. Freitas, C. A. P. S. Martins, "Simulation Tool of Network Processor for Learning Activities". Frontiers in Education Conference (FIE 2002), Boston, USA, 2002.
IBM PowerNP NP4GS3 Databook, http://www.ibm.com.
Intel W AN/LAN Access Switch Example Design for the Intel IXP 1200 Network Processor, May, 2001, http://www.intel.com.
Intel, "IXP 1200 - Network Processor", Datasheet, May 2000, http://www.intel.com.
Lexra, NetVortex Network Communications System Multiprocessor NPU, http://www.lexra.com.
M. Glesner, A. Kirschbaum, "State-of-the-Art in Rapid Prototyping", XI Brazilian Symposium on Integrated Circuit Design, SBCCI'98, Búzios, Rio de Janeiro, 1998, pp.60-65.
MMC Networks, "EPIF-105, EPIF-200, GPIF-207, XPIF-300, Packet Processors", http://www.mmcnet.com
Myrinet Overview, http://www.mvri.com/myrinet/overview/index.html.
Motorola's MPC8260 PowerQUICC li Integrated Communications Processor Family, Fact Sheet, 2001, http://www.motorola.com.
Patterson, O. A., J. L. Hennessy, Computer Organization and Design: The Hardware/Software Interface, Morgan Kaufmann Publisher, 1997.
Sitara Networks, QoS Solutions for Enterprise and Service Provider Markets, http://www.sitaranetworks.com.
Sitera IQ2000, Network Processor Product Brief, http://www.sitera.com.
T. H. Medeiros, C. A. P. S. Martins, "Reconf_KMT, Uma Ferramenta Reconfigurável para a Simulação de Microprocessadores", III Workshop de Sistemas Computacionais de Alto Desempenho, WSCAD'2002, Vitória - ES, 2002.
T. Wolf and J. Turner, "Design Issues for High Perfonnance Active Routers", International Zurich Seminar on Broadband Communications, Zurich, Switzerland, February 2000, pp. 199-205.
T. Wolf and M. A. Franklin, "CommBench - A Telecommunications Benchmark for Network Processors", International Symposiurn on Perfonnance Analysis of Systerns and Software (ISPASS), Austin, Texas, April 2000, pp. 154-162.
T. Wolf and M. A. Franklin, "Design of an Instruction Set for Modular Network Processors", IBM Research Report, RC2 1865, October 2000.
W. D. Mensch. Jr. and O. A. Silage, "System-on-chip Design Methodology in Engineering Education", International Conference on Engineering Education, ICEE2000 (IEEE/CS), Taipei, Taiwan, August 2000, pp. 224-228.
Agere System, Fast Pattern Processor (FPP) Product Brief, April 2001, http://www.agere.com.
Buya, R., High Perfonnance Cluster Cornputing, Volume 1, Prentice Hall, 1999.
Cisco 7200 Series Network Processor Family, NPE-400, NPE-300 and NPE-225, Datasheet, 2000, http://www.cisco.com.
Cisco Systems White Paper, "The Evolution of high-end Router Architectures-Basic Scalability and Performance Considerations for Evaluating Large-Scale Router Designs", 2001, http://www.cisco.com.
Cisco, Route Switch Processor 8 for Cisco 7500 Series Routers, Datasheet, 2000, http://www.cisco.com.
C-Port, C5e Network Processor Product Brief, January 2002, http://www.motorola.com.
C. Ulmer, C. Wood, S. Yalamanchili, "Active SANs: Hardware Support for Integrating Computation and Communication", Workshop on Novel Uses of System Arca Networks at HPCA (SAN 2002), February 2002.
D. L. Tennenhouse, J. M. Smith, W. D. Sincoskie, O. J. Wetherall, G. J. Minden, "A Survey of Active Network Research", IEEE Communications Magazine, Volume 35, N2 I, pp.80-86, 1997.
EZChip Network Processors, http://www.ezchip.com.
H. C. Freitas, C. A. P. S. Martins, "Processador de Rede com Suporte a Multi-protocolo e Topologias Dinâmicas", II Workshop de Sistemas Computacionais de Alto Desempenho, WSCAD'2001, Pirenópolis-GO, pp.31-38.
H. C. Freitas, C. A. P. S. Martins, "Projeto de Processador com Microarquitetura Dedicada para Roteamento em Sistemas de Comunicação de Dados", I Workshop de Sistemas Computacionais de Alto Desempenho, WSCAD'2000, São Pedro-SP, pp.63, (Iniciação Científica).
H. C. Freitas, C. A. P. S. Martins, "Simulation Tool of Network Processor for Learning Activities". Frontiers in Education Conference (FIE 2002), Boston, USA, 2002.
IBM PowerNP NP4GS3 Databook, http://www.ibm.com.
Intel W AN/LAN Access Switch Example Design for the Intel IXP 1200 Network Processor, May, 2001, http://www.intel.com.
Intel, "IXP 1200 - Network Processor", Datasheet, May 2000, http://www.intel.com.
Lexra, NetVortex Network Communications System Multiprocessor NPU, http://www.lexra.com.
M. Glesner, A. Kirschbaum, "State-of-the-Art in Rapid Prototyping", XI Brazilian Symposium on Integrated Circuit Design, SBCCI'98, Búzios, Rio de Janeiro, 1998, pp.60-65.
MMC Networks, "EPIF-105, EPIF-200, GPIF-207, XPIF-300, Packet Processors", http://www.mmcnet.com
Myrinet Overview, http://www.mvri.com/myrinet/overview/index.html.
Motorola's MPC8260 PowerQUICC li Integrated Communications Processor Family, Fact Sheet, 2001, http://www.motorola.com.
Patterson, O. A., J. L. Hennessy, Computer Organization and Design: The Hardware/Software Interface, Morgan Kaufmann Publisher, 1997.
Sitara Networks, QoS Solutions for Enterprise and Service Provider Markets, http://www.sitaranetworks.com.
Sitera IQ2000, Network Processor Product Brief, http://www.sitera.com.
T. H. Medeiros, C. A. P. S. Martins, "Reconf_KMT, Uma Ferramenta Reconfigurável para a Simulação de Microprocessadores", III Workshop de Sistemas Computacionais de Alto Desempenho, WSCAD'2002, Vitória - ES, 2002.
T. Wolf and J. Turner, "Design Issues for High Perfonnance Active Routers", International Zurich Seminar on Broadband Communications, Zurich, Switzerland, February 2000, pp. 199-205.
T. Wolf and M. A. Franklin, "CommBench - A Telecommunications Benchmark for Network Processors", International Symposiurn on Perfonnance Analysis of Systerns and Software (ISPASS), Austin, Texas, April 2000, pp. 154-162.
T. Wolf and M. A. Franklin, "Design of an Instruction Set for Modular Network Processors", IBM Research Report, RC2 1865, October 2000.
W. D. Mensch. Jr. and O. A. Silage, "System-on-chip Design Methodology in Engineering Education", International Conference on Engineering Education, ICEE2000 (IEEE/CS), Taipei, Taiwan, August 2000, pp. 224-228.
Publicado
28/10/2002
Como Citar
FREITAS, Henrique Cota de; MARTINS, Carlos Augusto Paiva da Silva.
R2NP: Processador de Rede RISC Reconfigurável. In: SIMPÓSIO EM SISTEMAS COMPUTACIONAIS DE ALTO DESEMPENHO (SSCAD), 3. , 2002, Vitória.
Anais [...].
Porto Alegre: Sociedade Brasileira de Computação,
2002
.
p. 60-67.
DOI: https://doi.org/10.5753/wscad.2002.20762.
