Aceleradores com CGRAs para Redes Reguladoras de Genes
Resumo
As redes reguladoras de genes são modelos usados para estudar a evolução e o comportamento celular. Uma rede pode ser representada por um grafo Booleano. Os algoritmos podem explorar paralelismo com a implementação dos grafos em FPGAs, porém devido a alta flexibilidade, o mapeamento para o FPGA pode demorar horas. Uma solução é usar um CGRA específico, que pode reduzir o tempo de mapeamento para poucos segundos, entretanto, esta abordagem gera novos desafios. Primeiro, as redes são grafos livres de escala. Segundo, as métricas de custo são diferentes dos CGRAs usuais. Este trabalho aplica a técnica de mapeamento de Simulated Annealing com novas funções de custo considerando especificidades das redes. Três padrões de interconexão foram avaliados para um conjunto de 21 redes reguladoras da literatura.Referências
Albert, I., Thakar, J., Li, S., Zhang, R., and Albert, R. (2008). Boolean network simulations for life scientists. Source code for biology and medicine, 3(1):1-8.
Aldana, M. (2003). Boolean dynamics of networks with scale-free topology. Physica D: Nonlinear Phenomena, 185(1):45-66.
Barabási, A.-L. (2009). Scale-free networks: a decade and beyond. science, 325(5939):412-413.
Bragança, L., Penha, J., Canesche, M., Ribeiro, D., Nacif, J. A. M., and Ferreira, R. (2021). An open-source cloud-fpga gene regulatory accelerator. In Anais do XXII Simpósio em Sistemas Computacionais de Alto Desempenho, pages 240-251. SBC.
Canesche, M., Menezes, M., Carvalho, W., Torres, F. S., Jamieson, P., Nacif, J. A., and Ferreira, R. (2020). Traversal: A fast and adaptive graph-based placement and routing for cgras. IEEE Trans on Computer-Aided Design of Integrated Circuits and Systems.
Carvalho, W., Canesche, M., Reis, L., Torres, F., Silva, L., Jamieson, P., Nacif, J., and Ferreira, R. (2020). A design exploration of scalable mesh-based fully pipelined accelerators. In International Conf on Field-Programmable Technology (ICFPT). IEEE.
da Silva, L. B., Almeida, D., Nacif, J. A. M., Sánchez-Osorio, I., Hernández-Martínez, C. A., and Ferreira, R. (2017). Exploring the dynamics of large-scale gene regulatory networks using hardware acceleration on a heterogeneous cpu-fpga platform. In IEEE Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig).
Ferreira, R., Denver, W., Pereira, M., Carro, L., and Wong, S. (2014). A run-time modulo scheduling by using a binary translation mechanism. In Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIV).
Ferreira, R. and Vendramini, J. (2010). Fpga-accelerated attractor computation of scale free gene regulatory networks. In Field Programmable Logic and Applications FPL.
Gowda, T. t. (2007). Threshold logic gene regulatory networks. In 2007 IEEE International Workshop on Genomic Signal Processing and Statistics, pages 1-4. IEEE.
Lee, C. Y. (1961). An algorithm for path connections and its applications. IRE transactions on electronic computers, (3):346-365.
Manica, M. t. (2019). Fpga accelerated analysis of boolean gene regulatory networks. IEEE/ACM Transactions on Computational Biology and Bioinformatics.
Miskov-Zivanov, N., Bresticker, A., Krishnaswamy, D., Kashinkunti, P., Marculescu, D., and Faeder, J. R. (2011). Regulatory network analysis acceleration with reconfigurable hardware. In IEEE Engineering in Medicine and Biology Society.
Murray, K. E., Petelin, O., Zhong, S., Wang, J. M., Sha, E., Graham, A. G., Wu, J., Walker, M. J., et al. (2020). Vtr 8: High-performance cad and customizable fpga architecture modelling. ACM Trans on Reconfigurable Technology and Systems (TRETS).
Silva, L. B. D., Ferreira, R., Canesche, M., Penha, J., Jamieson, P., and Nacif, J. A. M. (2019). Ready: A fine-grained multithreading overlay framework for modern cpu-fpga dataflow applications. ACM Transactions on Embedded Computing Systems (TECS).
UFV (2022). Grn. https://github.com/lesc-ufv/grn_hw_accelerator.
Vieira, M., Canesche, M., Bragança, L., Campos, J., Silva, M., Ferreira, R., and Nacif, J. A. (2021). Reshape: A run-time dataflow hardware-based mapping for cgra overlays. In International Symposium on Circuits and Systems (ISCAS). IEEE.
Zerarka, M., David, J., and Aboulhamid, E. (2004). High speed emulation of gene regulatory networks using fpgas. In Midwest Symp on Circuits and Systems. IEEE.
Aldana, M. (2003). Boolean dynamics of networks with scale-free topology. Physica D: Nonlinear Phenomena, 185(1):45-66.
Barabási, A.-L. (2009). Scale-free networks: a decade and beyond. science, 325(5939):412-413.
Bragança, L., Penha, J., Canesche, M., Ribeiro, D., Nacif, J. A. M., and Ferreira, R. (2021). An open-source cloud-fpga gene regulatory accelerator. In Anais do XXII Simpósio em Sistemas Computacionais de Alto Desempenho, pages 240-251. SBC.
Canesche, M., Menezes, M., Carvalho, W., Torres, F. S., Jamieson, P., Nacif, J. A., and Ferreira, R. (2020). Traversal: A fast and adaptive graph-based placement and routing for cgras. IEEE Trans on Computer-Aided Design of Integrated Circuits and Systems.
Carvalho, W., Canesche, M., Reis, L., Torres, F., Silva, L., Jamieson, P., Nacif, J., and Ferreira, R. (2020). A design exploration of scalable mesh-based fully pipelined accelerators. In International Conf on Field-Programmable Technology (ICFPT). IEEE.
da Silva, L. B., Almeida, D., Nacif, J. A. M., Sánchez-Osorio, I., Hernández-Martínez, C. A., and Ferreira, R. (2017). Exploring the dynamics of large-scale gene regulatory networks using hardware acceleration on a heterogeneous cpu-fpga platform. In IEEE Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig).
Ferreira, R., Denver, W., Pereira, M., Carro, L., and Wong, S. (2014). A run-time modulo scheduling by using a binary translation mechanism. In Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIV).
Ferreira, R. and Vendramini, J. (2010). Fpga-accelerated attractor computation of scale free gene regulatory networks. In Field Programmable Logic and Applications FPL.
Gowda, T. t. (2007). Threshold logic gene regulatory networks. In 2007 IEEE International Workshop on Genomic Signal Processing and Statistics, pages 1-4. IEEE.
Lee, C. Y. (1961). An algorithm for path connections and its applications. IRE transactions on electronic computers, (3):346-365.
Manica, M. t. (2019). Fpga accelerated analysis of boolean gene regulatory networks. IEEE/ACM Transactions on Computational Biology and Bioinformatics.
Miskov-Zivanov, N., Bresticker, A., Krishnaswamy, D., Kashinkunti, P., Marculescu, D., and Faeder, J. R. (2011). Regulatory network analysis acceleration with reconfigurable hardware. In IEEE Engineering in Medicine and Biology Society.
Murray, K. E., Petelin, O., Zhong, S., Wang, J. M., Sha, E., Graham, A. G., Wu, J., Walker, M. J., et al. (2020). Vtr 8: High-performance cad and customizable fpga architecture modelling. ACM Trans on Reconfigurable Technology and Systems (TRETS).
Silva, L. B. D., Ferreira, R., Canesche, M., Penha, J., Jamieson, P., and Nacif, J. A. M. (2019). Ready: A fine-grained multithreading overlay framework for modern cpu-fpga dataflow applications. ACM Transactions on Embedded Computing Systems (TECS).
UFV (2022). Grn. https://github.com/lesc-ufv/grn_hw_accelerator.
Vieira, M., Canesche, M., Bragança, L., Campos, J., Silva, M., Ferreira, R., and Nacif, J. A. (2021). Reshape: A run-time dataflow hardware-based mapping for cgra overlays. In International Symposium on Circuits and Systems (ISCAS). IEEE.
Zerarka, M., David, J., and Aboulhamid, E. (2004). High speed emulation of gene regulatory networks using fpgas. In Midwest Symp on Circuits and Systems. IEEE.
Publicado
19/10/2022
Como Citar
BARROS, Olavo; RONDOW, Caio Von; PENHA, Jeronimo; CANESCHE, Michael; NACIF, José Augusto M.; FERREIRA, Ricardo.
Aceleradores com CGRAs para Redes Reguladoras de Genes. In: SIMPÓSIO EM SISTEMAS COMPUTACIONAIS DE ALTO DESEMPENHO (SSCAD), 23. , 2022, Florianópolis/SC.
Anais [...].
Porto Alegre: Sociedade Brasileira de Computação,
2022
.
p. 229-240.
DOI: https://doi.org/10.5753/wscad.2022.226375.
