From Code to RTL: A Methodology for Analyzing the HLS Hardware Generation Process

• Henrique Gregory Gimenez USP
• Edson Toshimi Midorikawa USP
• Felipe Valencia de Almeida USP
• Liria Matsumoto Sato USP

DOI: https://doi.org/10.5753/sscad.2026.34690

Resumo

High-Level Synthesis (HLS) abstracts the hardware accelerator design process, but evaluating the generated RTL often becomes a “black-box” challenge for developers. To address this issue, we propose a systematic methodology to track and analyze the translation of C/C++ algorithms into hardware (RTL). Our approach integrates synthesis via Xilinx Vitis/Vivado 2024.2 with datapath mapping using Intel Quartus and behavioral waveform validation via ModelSim. By applying this methodology to different algorithms, we mapped how the compiler translates constant complexity codes into linear pipelines and iterative logic into multi-stage Finite State Machines (FSMs). To evaluate the architectural results extracted by our method, we conducted performance evaluations on a PYNQ-Z2 board. Experimental results show that while the hardware reduces clock cycles, the absolute speedup is constrained by communication overhead. We conclude that the proposed methodology provides a replicable pathway for developers to understand the HLS-to-RTL mapping.

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