Arquitetura de FPGA para Inferência Bit-Exata de GBDTs com Árvores Simétricas
Resumo
Este trabalho propõe um método para mapear diretamente ensembles de Gradient Boosted Decision Trees (GBDT) com árvores simétricas em primitivas LUT (lookup table) de FPGA. A arquitetura combina um banco de comparadores compartilhado, ROMs de valores de folha e uma árvore de somadores balanceada, formando um caminho combinacional de inferência com pipeline opcional. O método proposto integra regularização de predicados orientada ao hardware, árvores multi-output com splits compartilhados, quantização integrada ao treinamento, precisão adaptativa por iteração e otimizações pós-treinamento das ROMs para reduzir o custo em hardware, preservando o desempenho preditivo. Um fluxo automatizado gera VHDL sintetizável e valida equivalência bit a bit por simulação GHDL. No JSC, a arquitetura atinge 74,56% de acurácia com 799 LUTs e, no MNIST, 96,44% com 4.495 LUTs, demonstrando acurácia competitiva com baixo uso de recursos de FPGA.
Referências
Andronic, M. and Constantinides, G. A. (2023). Polylut: Learning piecewise polynomials for ultra-low latency fpga lut-based inference. In International Conference on Field Programmable Technology (ICFPT), pages 60–68.
Andronic, M. and Constantinides, G. A. (2024). Neuralut: Hiding neural network density in boolean synthesizable functions. In International Conference on Field-Programmable Logic and Applications (FPL), pages 140–148.
Andronic, M. and Constantinides, G. A. (2025). Neuralut-assemble: Hardware-aware assembling of sub-neural networks for efficient lut inference. arXiv preprint arXiv:2504.00592.
Bacellar, A. T. L., Susskind, Z., Breternitz Jr, M., John, E., John, L. K., Lima, P. M. V., and França, F. M. G. (2024). Differentiable weightless neural networks. In Proceedings of the 41st International Conference on Machine Learning (ICML), volume 235, pages 2277–2295.
Cassidy, O., Andronic, M., Coward, S., and Constantinides, G. A. (2025). Reduce-dLUT: Table decomposition with “don’t care” conditions. In Proceedings of the 2025 ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA ’25). arXiv:2412.18579.
Chen, T. and Guestrin, C. (2016). XGBoost: A scalable tree boosting system. In ACM SIGKDD International Conference on Knowledge Discovery and Data Mining, pages 785–794.
CMS Collaboration (2020). The phase-2 upgrade of the cms level-1 trigger. Technical Report CERN-LHCC-2020-004, CERN, Geneva.
Duarte, J. et al. (2018). Fast inference of deep neural networks in FPGAs for particle physics. Journal of Instrumentation, 13:P07027. Introduces the hls4ml lhc jets hlf (JSC) dataset, OpenML ID 42468.
Fahim, F. et al. (2021). hls4ml: An open-source codesign workflow to empower scientific low-power machine learning devices. arXiv preprint arXiv:2103.05579.
Friedman, J. H. (2001). Greedy function approximation: A gradient boosting machine. Annals of Statistics, 29(5):1189–1232.
Khataei, A. and Bazargan, K. (2025). TreeLUT: An efficient alternative to deep neural networks for inference acceleration using gradient boosted decision trees. In Proceedings of the 2025 ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA ’25), pages 1–11. arXiv:2501.01511.
LeCun, Y., Bottou, L., Bengio, Y., and Haffner, P. (1998). Gradient-based learning applied to document recognition. Proceedings of the IEEE, 86(11):2278–2324.
Lou, B., Rademacher, R., Boland, D., and Leong, P. H. W. (2024). Polylut-add: Fpga-based lut inference with wide inputs. In International Conference on Field-Programmable Logic and Applications (FPL), pages 149–155.
Prokhorenkova, L., Gusev, G., Vorobev, A., Dorogush, A. V., and Gulin, A. (2018). Cat-Boost: Unbiased boosting with categorical features. Advances in Neural Information Processing Systems (NeurIPS), 31.
Summers, S. et al. (2020). Fast inference of boosted decision trees in fpgas for particle physics. Journal of Instrumentation, 15:P05026.
Umuroglu, Y., Akhauri, Y., Fraser, N. J., and Blott, M. (2020). Logicnets: Co-designed neural networks and circuits for extreme-throughput applications. In International Conference on Field-Programmable Logic and Applications (FPL).
Yates, B. R. and CMS Collaboration (2021). A cms level-1 track finder for the hl-lhc. arXiv preprint arXiv:2110.02826.
Andronic, M. and Constantinides, G. A. (2024). Neuralut: Hiding neural network density in boolean synthesizable functions. In International Conference on Field-Programmable Logic and Applications (FPL), pages 140–148.
Andronic, M. and Constantinides, G. A. (2025). Neuralut-assemble: Hardware-aware assembling of sub-neural networks for efficient lut inference. arXiv preprint arXiv:2504.00592.
Bacellar, A. T. L., Susskind, Z., Breternitz Jr, M., John, E., John, L. K., Lima, P. M. V., and França, F. M. G. (2024). Differentiable weightless neural networks. In Proceedings of the 41st International Conference on Machine Learning (ICML), volume 235, pages 2277–2295.
Cassidy, O., Andronic, M., Coward, S., and Constantinides, G. A. (2025). Reduce-dLUT: Table decomposition with “don’t care” conditions. In Proceedings of the 2025 ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA ’25). arXiv:2412.18579.
Chen, T. and Guestrin, C. (2016). XGBoost: A scalable tree boosting system. In ACM SIGKDD International Conference on Knowledge Discovery and Data Mining, pages 785–794.
CMS Collaboration (2020). The phase-2 upgrade of the cms level-1 trigger. Technical Report CERN-LHCC-2020-004, CERN, Geneva.
Duarte, J. et al. (2018). Fast inference of deep neural networks in FPGAs for particle physics. Journal of Instrumentation, 13:P07027. Introduces the hls4ml lhc jets hlf (JSC) dataset, OpenML ID 42468.
Fahim, F. et al. (2021). hls4ml: An open-source codesign workflow to empower scientific low-power machine learning devices. arXiv preprint arXiv:2103.05579.
Friedman, J. H. (2001). Greedy function approximation: A gradient boosting machine. Annals of Statistics, 29(5):1189–1232.
Khataei, A. and Bazargan, K. (2025). TreeLUT: An efficient alternative to deep neural networks for inference acceleration using gradient boosted decision trees. In Proceedings of the 2025 ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA ’25), pages 1–11. arXiv:2501.01511.
LeCun, Y., Bottou, L., Bengio, Y., and Haffner, P. (1998). Gradient-based learning applied to document recognition. Proceedings of the IEEE, 86(11):2278–2324.
Lou, B., Rademacher, R., Boland, D., and Leong, P. H. W. (2024). Polylut-add: Fpga-based lut inference with wide inputs. In International Conference on Field-Programmable Logic and Applications (FPL), pages 149–155.
Prokhorenkova, L., Gusev, G., Vorobev, A., Dorogush, A. V., and Gulin, A. (2018). Cat-Boost: Unbiased boosting with categorical features. Advances in Neural Information Processing Systems (NeurIPS), 31.
Summers, S. et al. (2020). Fast inference of boosted decision trees in fpgas for particle physics. Journal of Instrumentation, 15:P05026.
Umuroglu, Y., Akhauri, Y., Fraser, N. J., and Blott, M. (2020). Logicnets: Co-designed neural networks and circuits for extreme-throughput applications. In International Conference on Field-Programmable Logic and Applications (FPL).
Yates, B. R. and CMS Collaboration (2021). A cms level-1 track finder for the hl-lhc. arXiv preprint arXiv:2110.02826.
Publicado
03/11/2026
Como Citar
NUNES, Marcus V. S.; FERNANDES, Marcelo A. C..
Arquitetura de FPGA para Inferência Bit-Exata de GBDTs com Árvores Simétricas. In: SIMPÓSIO EM SISTEMAS COMPUTACIONAIS DE ALTO DESEMPENHO (SSCAD), 27. , 2026, Natal/RN.
Anais [...].
Porto Alegre: Sociedade Brasileira de Computação,
2026
.
p. 165-177.
DOI: https://doi.org/10.5753/sscad.2026.34888.
