A Tile-Based BLAS Library for Tenstorrent Dataflow Architectures

• Calebe P. Bianchini CESAR Innovation Center / UPM
• Evaldo Costa CESAR Innovation Center
• Felipe Portella PETROBRAS
• Gabriel Freytag CESAR Innovation Center
• Jeferson S. Rocha PETROBRAS
• Leon Barboza CESAR Innovation Center
• Maicon M. Alves PETROBRAS
• Rodrigo Machado CESAR Innovation Center
• Vinícius Ventura CESAR Innovation Center

DOI: https://doi.org/10.5753/sscad.2026.34997

Resumo

Emerging AI accelerators increasingly adopt spatial and dataflow execution models based on distributed compute units, local memories, and explicit data movement. Although primarily designed for machine learning, these architectures are also being explored for scientific computing. This paper presents a tile-based BLAS library for Tenstorrent dataflow architectures, mapping representative Level-1, Level-2, and Level-3 operations onto Tensix cores through tiled layouts, circular buffers, explicit DRAM–SRAM movement, and local data reuse. We describe the main design decisions required by this execution model, including data layout, kernel decomposition, synchronization, data-format constraints, and workload distribution. The library is evaluated on a dual-ASIC Wormhole™ n300 accelerator using device-side profiling in single-chip and dual-chip configurations. AXPY and GER show sublinear multichip scaling, whereas GEMM benefits more strongly from the second ASIC, reaching a maximum measured throughput of 5.79 TFLOP/s and an observed maximum speedup of 2.07×. The results show that tile organization, data movement, arithmetic intensity, and workload distribution strongly influence BLAS performance and multichip scaling on Tenstorrent accelerators.

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