Performance Evaluation of Intel and AMD Memory Hierarchies Using a Simulation-driven Approach With Gem5
Resumo
Along with the necessity of more computational power, CPUs are evolving quickly. Companies are developing new generations of CPUs every 1–2 years, and many options compete for market share. Hence, researchers and companies must develop a method to compare and select the best processor that fits their needs. This paper presents a simulation-driven alternative for CPU Memory Hierarchy evaluation and comparison. Furthermore, this work compares two rival processors engineered by Intel and AMD. The investigation culminates in the observation that AMD’s processor performs better with fewer cores for several cases, while Intel’s equivalent exhibits enhanced results when all available cores are used.
Referências
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Ayaz Akram et al. Validation of the gem5 simulator for x86 architectures. In 2019 IEEE/ACM Performance Modeling, Benchmarking and Simulation of High Performance Computer Systems (PMBS), pages 53–58, 2019b.
Nathan Binkert et al. The gem5 simulator. SIGARCH Comput. Archit. News, 39(2):1–7, aug 2011. ISSN 0163-5964.
Trevor E. Carlson et al. Sniper: Exploring the level of abstraction for scalable and accurate parallel multi-core simulation. In SC ’11: Proceedings of 2011 Int. Conf. for High Performance Computing, Networking, Storage and Analysis, pages 1–12, 2011.
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Matheus A. Souza et al. Cap bench: a benchmark suite for performance and energy evaluation of low-power many-core processors. Concurrency and Computation: Practice and Experience, 29(4):e3892, 2017a.
Matheus A. Souza et al. Energy consumption improvement of shared-cache multicore clusters based on explicit simultaneous multithreading. In 2017 Int. Symposium on Computer Architecture and High Performance Computing Workshops (SBAC-PADW), pages 1–6, 2017b.
Matheus A. Souza et al. Design space exploration of energy efficient noc-and cache-based many-core architecture. In 2018 30th Int. Symposium on Computer Architecture and High Performance Computing (SBAC-PAD), pages 402–409, 2018.
Rafael Ubal et al. Multi2sim: A simulation framework to evaluate multicore-multithreaded processors. In 19th Int. Symposium on Computer Architecture and High Performance Computing (SBAC-PAD’07), pages 62–68, 2007.
Johnson Umeike et al. Profiling gem5 simulator. In 2023 IEEE Int. Symposium on Performance Analysis of Systems and Software (ISPASS), pages 103–113, 2023.
B. Vikas et al. On the cache behavior of splash-2 benchmarks on arm and alpha processors in gem5 full system simulator. In 2014 3rd Int. Conf. on Eco-friendly Computing and Communication Systems, pages 5–8, 2014.
Matt T. Yourst. Ptlsim: A cycle accurate full system x86-64 microarchitectural simulator. In 2007 IEEE Int. Symposium on Performance Analysis of Systems Software, pages 23–34, 2007.
Ayaz Akram et al. ×86 computer architecture simulators: A comparative study. In 2016 IEEE 34th Int. Conf. on Computer Design (ICCD), pages 638–645, 2016.
Ayaz Akram et al. A survey of computer architecture simulation techniques and tools. IEEE Access, 7:78120–78145, 2019a.
Ayaz Akram et al. Validation of the gem5 simulator for x86 architectures. In 2019 IEEE/ACM Performance Modeling, Benchmarking and Simulation of High Performance Computer Systems (PMBS), pages 53–58, 2019b.
Nathan Binkert et al. The gem5 simulator. SIGARCH Comput. Archit. News, 39(2):1–7, aug 2011. ISSN 0163-5964.
Trevor E. Carlson et al. Sniper: Exploring the level of abstraction for scalable and accurate parallel multi-core simulation. In SC ’11: Proceedings of 2011 Int. Conf. for High Performance Computing, Networking, Storage and Analysis, pages 1–12, 2011.
Subodha Charles et al. Exploration of memory and cluster modes in directory-based many-core cmps. In 2018 Twelfth IEEE/ACM Int. Symposium on Networks-on-Chip (NOCS), pages 1–8, 2018.
Daniel Chavarría-Miranda et al. High-performance computing (hpc): Application use in the power grid. In 2012 IEEE Power and Energy Society General Meeting, pages 1–7, 2012.
Fernando A. Endo et al. Micro-architectural simulation of in-order and out-of-order arm microprocessors with gem5. In 2014 Int. Conf. on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIV), pages 266–273, 2014.
Matheus A. Souza et al. Cap bench: a benchmark suite for performance and energy evaluation of low-power many-core processors. Concurrency and Computation: Practice and Experience, 29(4):e3892, 2017a.
Matheus A. Souza et al. Energy consumption improvement of shared-cache multicore clusters based on explicit simultaneous multithreading. In 2017 Int. Symposium on Computer Architecture and High Performance Computing Workshops (SBAC-PADW), pages 1–6, 2017b.
Matheus A. Souza et al. Design space exploration of energy efficient noc-and cache-based many-core architecture. In 2018 30th Int. Symposium on Computer Architecture and High Performance Computing (SBAC-PAD), pages 402–409, 2018.
Rafael Ubal et al. Multi2sim: A simulation framework to evaluate multicore-multithreaded processors. In 19th Int. Symposium on Computer Architecture and High Performance Computing (SBAC-PAD’07), pages 62–68, 2007.
Johnson Umeike et al. Profiling gem5 simulator. In 2023 IEEE Int. Symposium on Performance Analysis of Systems and Software (ISPASS), pages 103–113, 2023.
B. Vikas et al. On the cache behavior of splash-2 benchmarks on arm and alpha processors in gem5 full system simulator. In 2014 3rd Int. Conf. on Eco-friendly Computing and Communication Systems, pages 5–8, 2014.
Matt T. Yourst. Ptlsim: A cycle accurate full system x86-64 microarchitectural simulator. In 2007 IEEE Int. Symposium on Performance Analysis of Systems Software, pages 23–34, 2007.
Publicado
17/10/2023
Como Citar
VIEIRA, João Victor Amorim; SOUZA, Matheus Alcântara; FREITAS, Henrique Cota de.
Performance Evaluation of Intel and AMD Memory Hierarchies Using a Simulation-driven Approach With Gem5. In: WORKSHOP DE INICIAÇÃO CIENTÍFICA - SIMPÓSIO EM SISTEMAS COMPUTACIONAIS DE ALTO DESEMPENHO (SSCAD), 24. , 2023, Porto Alegre/RS.
Anais [...].
Porto Alegre: Sociedade Brasileira de Computação,
2023
.
p. 17-24.
DOI: https://doi.org/10.5753/wscad_estendido.2023.235791.
