Analysis of branch prediction techniques under the RISC-V architecture

• Lucas Arruk Mendes UFSCar
• Maurício Figueiredo UFSCar
• Ricardo Menotti UFSCar

DOI: https://doi.org/10.5753/sscad_estendido.2024.244790

Abstract

Branch prediction is a critical technique for enhancing the performance of pipelined processors by minimizing the penalties associated with control hazards. This paper presents a comparative analysis of branch prediction models implemented in a RISC-V processor architecture, focusing on Bimodal, Gselect, and Gshare predictors. Each model was designed, implemented, and tested on an FPGA platform to evaluate its accuracy, resource utilization, and impact on overall processor performance.

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