Evaluation of the Impact of Coherence Protocols and Cache Sizes on Parallel Algorithms Through Simulations
Resumo
This article explores the intersection between parallel algorithms and cache optimization, focusing on how different coherence protocols and cache sizes impact the performance of parallel algorithms. Through simulations, we evaluate the efficiency of parallel algorithms under various cache configurations. Our goal is to understand the implications of these configurations and identify optimal strategies for cache utilization. The results of this study provide valuable insights for computational performance optimization in the modern era of technology.Referências
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Handy, J. (1998). The cache memory book (2nd ed.): the authoritative reference on cache design. Academic Press, Inc., USA.
Kaushik, A. M., Hassan, M., and Patel, H. (2021). Designing predictable cache coherence protocols for multi-core real-time systems. IEEE Transactions on Computers, 70(12):2098–2111.
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Ramtake, D., Singh, N., Kumar, S., and Patle, V. K. (2020). Cache associativity analysis of multicore systems. In Int. Conf. on Comp. Science, Eng. & Applications, pages 1–4.
Rattanatranurak, A. and Kittitornkun, S. (2020). A parallel triple-pivot sorting (ptpsort) algorithm: Preliminary results. In 17th Int. Conf. on Electrical Eng./Electronics, Computer, Telecom. and I.T., pages 59–62.
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Yavits, L., Morad, A., and Ginosar, R. (2014). Cache hierarchy optimization. IEEE Computer Architecture Letters, 13(2):69–72.
Zhu, M., Shahab, A., Katsarakis, A., and Grot, B. (2021). Invalidate or update? revisiting coherence for tomorrow’s cache hierarchies. In 30th International Conference on Parallel Architectures and Compilation Techniques, pages 226–241.
Fang, J. et al. (2017). Performance optimization by dynamically altering cache replacement algorithm in cpu-gpu heterogeneous multi-core architecture. In IEEE/ACM Int. Symp. on Cluster, Cloud and Grid Computing, pages 723–726.
Handy, J. (1998). The cache memory book (2nd ed.): the authoritative reference on cache design. Academic Press, Inc., USA.
Kaushik, A. M., Hassan, M., and Patel, H. (2021). Designing predictable cache coherence protocols for multi-core real-time systems. IEEE Transactions on Computers, 70(12):2098–2111.
Lowe-Power, J. et al. (2020). The gem5 simulator: Version 20.0+.
Patterson, D. A. and Hennessy, J. L. (1990). Computer architecture: a quantitative approach. MK Publishers Inc., San Francisco, CA, USA.
Patterson, D. A. and Hennessy, J. L. (2013). Computer Organization and Design: The Hardware/Software Interface. MK Publishers Inc., San Francisco, CA, USA.
Ramtake, D., Singh, N., Kumar, S., and Patle, V. K. (2020). Cache associativity analysis of multicore systems. In Int. Conf. on Comp. Science, Eng. & Applications, pages 1–4.
Rattanatranurak, A. and Kittitornkun, S. (2020). A parallel triple-pivot sorting (ptpsort) algorithm: Preliminary results. In 17th Int. Conf. on Electrical Eng./Electronics, Computer, Telecom. and I.T., pages 59–62.
Stallings, W. (2010). Computer Organization and Architecture: Designing for Performance. Prentice Hall.
Yavits, L., Morad, A., and Ginosar, R. (2014). Cache hierarchy optimization. IEEE Computer Architecture Letters, 13(2):69–72.
Zhu, M., Shahab, A., Katsarakis, A., and Grot, B. (2021). Invalidate or update? revisiting coherence for tomorrow’s cache hierarchies. In 30th International Conference on Parallel Architectures and Compilation Techniques, pages 226–241.
Publicado
23/10/2024
Como Citar
FAGUNDES, Guilherme Dantas C.; SOUZA, Matheus Alcântara.
Evaluation of the Impact of Coherence Protocols and Cache Sizes on Parallel Algorithms Through Simulations. In: WORKSHOP DE INICIAÇÃO CIENTÍFICA - SIMPÓSIO EM SISTEMAS COMPUTACIONAIS DE ALTO DESEMPENHO (SSCAD), 25. , 2024, São Carlos/SP.
Anais [...].
Porto Alegre: Sociedade Brasileira de Computação,
2024
.
p. 17-24.
DOI: https://doi.org/10.5753/sscad_estendido.2024.244058.