Interactive shell with loader for RISC-V on FPGA

  • Luiz Carlos da S. N. Vartuli UnB
  • Marcus Vinicius Lamar UnB
  • Alba Cristina M. A. de Melo UnB
DOI: https://doi.org/10.5753/sscad_estendido.2025.15937

Abstract


This work presents the development of a shell for a RISC-V processor implemented on an FPGA with extremely limited memory. The system enables loading and executing programs via an RS232 serial interface, replacing the use of the Intel Quartus® Prime In-System Memory Content Editor. The text interface follows the REPL model and includes commands such as echo, clear, help, exit, and exec, which loads binary files directly into memory. Tests confirmed the shell’s functionality, including error handling and compatibility with the RISC-V Assembler and Runtime Simulator (RARS).

References

Fernandes, J. H. F. (2021). Bootloader for a RISC-V processor that uses Flash Memory. Master’s thesis, Instituto Superior Técnico.

Ministério da Ciência, Tecnologia e Inovação (2024). Brasil se torna membro da Aliança RISC-V International. [link].

Pelé, A.-F. (2025). CEA Backs RISC-V for Sovereign, Scalable Computing. [link].

Terasic Technologies (2025). DE1-SoC Development Kit. [link]. Accessed: 2025-06-29.

Valente, L., Tortorella, Y., Sinigaglia, M., Tagliavini, G., Capotondi, A., Benini, L., and Rossi, D. (2023). HULK-V: a Heterogeneous Ultra-low-power Linux capable RISC-V SoC. In 2023 Design, Automation & Test in Europe Conference & Exhibition (DATE), pages 1–6.
Published
2025-10-28
How to Cite

Select a Format
VARTULI, Luiz Carlos da S. N.; LAMAR, Marcus Vinicius; MELO, Alba Cristina M. A. de. Interactive shell with loader for RISC-V on FPGA. In: UNDERGRADUATE RESEARCH WORKSHOP - SYMPOSIUM ON HIGH PERFORMANCE COMPUTING SYSTEMS (SSCAD), 26. , 2025, Bonito/MS. Anais [...]. Porto Alegre: Sociedade Brasileira de Computação, 2025 . p. 41-48. DOI: https://doi.org/10.5753/sscad_estendido.2025.15937.