Evaluating L4S Framework Performance with Programmable Data Plane Hardware

• Leandro C. de Almeida IFPB
• Paulo Ditarso Maciel Jr. IFPB
• Fábio L. Verdi UFSCar

DOI: https://doi.org/10.5753/wgrs.2024.3286

Resumo

L4S, which stands for Low Latency, Low Loss, Scalable Throughput, is an initiative within the Internet Engineering Task Force (IETF) dedicated to enhancing the performance of real-time interactive applications across the Internet, like online gaming, video conferencing, and virtual reality. Its core principles revolve around implementing a novel variant of congestion control (CC) algorithm on end hosts and deploying an Active Queue Management (AQM) scheme on network nodes. Evaluating AQM algorithm adherence within the L4S framework on conventional network devices is challenging due to limited access to implementation details. However, the game changed with the introduction of data plane programmability, which facilitates the incorporation of intelligence during packet processing at the hardware’s most proximate level, without the necessity for control plane intervention. In this context, this paper evaluates the implementation of two key L4S-capable algorithms, iRED and PI2, using a real hardware P4-capable switch (Tofino2). The evaluation aims to verify the adherence of these algorithms to the L4S framework and observe their coexistence with non-L4S flows. Through controlled variations in bandwidth and delay, we assess the “goodput” metric to understand under what conditions iRED and PI2 demonstrate enhanced fairness.

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