Programming Practices for Cache Memory Optimization with Relevance to Embedded Systems: A Scoping Review

• Ramiro V. dos Santos Júnior UFERSA
• Francisco Rafael B. de Sousa UERN
• José Inácio M. Ferreira UERN
• Raul B. Paradeda UERN

DOI: https://doi.org/10.5753/wperformance.2026.21675

Resumo

Cache memory efficiency is a cornerstone of performance in computing systems, particularly in embedded applications where hardware resources are constrained. While research on cache replacement and reconfiguration algorithms is well established, software-level programming practices designed to optimize memory hierarchy utilization remain underexplored. This paper presents a scoping review conducted in accordance with PRISMA-ScR guidelines to map evidence on programming techniques that directly enhance cache locality and performance in embedded systems. Empirical studies published between 2015 and 2025 were retrieved from IEEE Xplore, ACM Digital Library, ScienceDirect, and the CAPES Portal. From an initial pool of 2,609 studies, 11 were selected after applying eligibility criteria based on open-access availability, relevance to software-level cache practices, and the presence of empirical results. The selected studies were organized into four thematic categories: data layout and reordering, loop transformations, memory alignment and range propagation, and cache-aware scheduling. Across heterogeneous experimental settings, reported gains demonstrate significant improvements in speedup and energy reduction, depending on workload, platform, and measurement method. Finally, this review identifies existing research gaps and outlines directions for future investigation, including integrating identified techniques into compiler infrastructure and evaluating them on embedded Artificial Intelligence workloads.

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