Implementation of Techniques for Fault Tolerance in a Network-on-Chip

  • Fabricio Veiga Universidade do Vale do Itajaí
  • Cesar Albenes Zeferino Universidade do Vale do Itajaí


Networks-on-Chip (NoCs - Networks-on-Chip) have emerged as the best alternative to provide high performance in communication for futures Systems-on- Chip (SoCs) with dozens of cores integrated on a single silicon die. However, the components of a NoC are susceptible to faults resulting from heating, power surge, external radiation and others. Faults in a router or a network link can lead to the transfer of erroneous data or, depending on the nature of the fault, cause problems in routing packets, such as forwarding a packet to an incorrect destination or even prevention of a particular path network is used, resulting in system failures. A fault tolerant NoC should be able to detect a fault and prevent it from leading to a system failure, ensuring the correct operation of the application. This paper presents the implementation of techniques for detection and recovery of faults in a NoC, which were modeled in SystemC and validated by simulation. Results compare the effectiveness of two techniques to provide fault tolerance to a NoC.
Palavras-chave: Irrigation, Crosstalk, System-on-a-chip, Integrated circuit modeling, Circuit faults, Fault tolerance, Fault tolerant systems
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VEIGA, Fabricio; ZEFERINO, Cesar Albenes. Implementation of Techniques for Fault Tolerance in a Network-on-Chip. In: SIMPÓSIO EM SISTEMAS COMPUTACIONAIS DE ALTO DESEMPENHO (SSCAD), 11. , 2010, Petrópolis. Anais [...]. Porto Alegre: Sociedade Brasileira de Computação, 2010 . p. 80-87.