LTMS: Um escalonador NUMA-Aware para STM

  • Michael Alexandre Costa UFPel
  • Tiago Perlin UFPel / IFFar
  • André Rauber Du Bois UFPel
  • Gerson Cavalheiro UFPel

Resumo


As transações em sistemas com Memória Transacional são, usualmente, realizadas de forma otimista, de forma a promover a exploração do paralelismo do hardware, mas aumentando a probabilidade de conflitos nos acessos. Neste trabalho é proposta uma estratégia de escalonamento baseada na migração de threads entre núcleos de processamento, apoiada pela observação da localidade de referência de acesso à memória dos threads em execução. Em experimentos realizados com o benchmark STAMP, para a maioria das aplicações, o escalonador proposto produziu menor taxa de aborts e menor tempo de execução em função do agrupamento de threads conforme a possibilidade de conflitos e o custo no acesso à memória.

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Publicado
19/10/2022
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COSTA, Michael Alexandre; PERLIN, Tiago; DU BOIS, André Rauber; CAVALHEIRO, Gerson. LTMS: Um escalonador NUMA-Aware para STM. In: SIMPÓSIO EM SISTEMAS COMPUTACIONAIS DE ALTO DESEMPENHO (WSCAD), 23. , 2022, Florianópolis/SC. Anais [...]. Porto Alegre: Sociedade Brasileira de Computação, 2022 . p. 37-48. DOI: https://doi.org/10.5753/wscad.2022.226303.