MuTARe: A Multi-Target, Adaptive Reconfigurable Architecture

  • Marcelo Brandalero UFRGS
  • Luigi Carro UFRGS
  • Antonio Carlos Schneider Beck UFRGS


With recent changes in transistor scaling trends, the design of all types of processing systems has become increasingly constrained by power consumption. At the same time, driven by the needs of fast response times, many applications are migrating from the cloud to the edge, pushing for the challenge of increasing the performance of these already power-constrained devices. The key to addressing this problem is to design application-specific processors that perfectly match the application's requirements and avoid unnecessary energy consumption. However, such dedicated platforms require significant design time and are thus unable to match the pace of fast-evolving applications that are deployed in the Internet-of-Things (IoT) every day. Motivated by the need for high energy efficiency and high flexibility in hardware platforms, this thesis paves the way to a new class of low-power adaptive processors that can achieve these goals by automatically modifying their structure at run time to match different applications' resource requirements. The proposed Multi-Target Adaptive Reconfigurable Architecture (MuTARe) is based upon a Coarse-Grained Reconfigurable Architecture (CGRA) that can transparently accelerate already-deployed applications, but incorporates novel compute paradigms such as Approximate Computing (AxC) and Near-Threshold Voltage Computing (NTC) to improve its efficiency. Compared to a traditional system of heterogeneous processing cores (similar to ARM's big.LITTLE), the base MuTARe architecture can (without any change to the existing software) improve the execution time by up to $1.3\times$, adapt to the same task deadline with $1.6\times$ smaller energy consumption or adapt to the same low energy budget with $2.3\times$ better performance. When extended for AxC, MuTARe's power savings can be further improved by up to $50\%$ in error-tolerant applications, and when extended for NTC, MuTARe can save further $30\%$ energy in memory-intensive workloads.

Palavras-chave: Computer architecture, reconfigurable architecture, adaptable architecture, approximate computing, near-threshold voltage computing


Adegbija, T., Rogacs, A., Patel, C., and Gordon-Ross, A. (2018). Microprocessor optimizations for the internet of things: A survey. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 37(1):7-20.

Beck, A. C. S., Rutzig, M. B., and Carro, L. (2014). A transparent and adaptive reconfigurable system. Elsevier Microprocessors and Microsystems, 38(5):509-524.

Bonomi, F., Milito, R., Zhu, J., and Addepalli, S. (2012). Fog computing and its role in the internet of things. In MCC Workshop on Mobile Cloud Computing, pages 13-16.

Dean, J., Patterson, D., and Young, C. (2018). A new golden age in computer architecture: Empowering the machine-learning revolution. IEEE Micro, 38(2):21-29.

Esmaeilzadeh, H., Blem, E., Amant, R. S., Sankaralingam, K., and Burger, D. (2012). Dark silicon and the end of multicore scaling. IEEE Micro, 32(3):122-134.

Mittal, S. (2015). A Survey of Architectural Techniques for Near-Threshold Computing. ACM Computing Surveys, 12(4):1-26.

Mittal, S. (2016). A Survey of Techniques for Approximate Computing. ACM Computing Surveys, 48(4):1-33.

Patterson, D. (2018). 50 years of computer architecture: From the mainframe cpu to the domain-specific tpu and the open risc-v instruction set. In IEEE ISSCC, pages 27-31.

Rahimi, A., Benini, L., and Gupta, R. K. (2016). Variability Mitigation in Nanometer CMOS Integrated Systems: A Survey of Techniques From Circuits to Software. Proceedings of the IEEE, 104(7):1410-1448.
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BRANDALERO, Marcelo; CARRO, Luigi; BECK, Antonio Carlos Schneider. MuTARe: A Multi-Target, Adaptive Reconfigurable Architecture. In: CONCURSO DE TESES E DISSERTAÇÕES (CTD), 33. , 2020, Cuiabá. Anais [...]. Porto Alegre: Sociedade Brasileira de Computação, 2020 . p. 19-24. ISSN 2763-8820. DOI: