Shared Memory Verification for Multicore Chip Designs

• Marleson Graf UFSC http://orcid.org/0000-0003-3636-1126
• Luiz C. V. dos Santos UFSC http://orcid.org/0000-0002-9384-8347

DOI: https://doi.org/10.5753/ctd.2021.15760

Resumo

A multicore chip usually provides a shared memory abstraction implemented by a cache coherence protocol. On-chip coherence can scale gracefully as the number of cores grows, and it plays a major role for general purpose applications. Besides, multicore architectures are likely to relax constraints on store atomicity and on the ordering between loads and stores. As a result, the validation of shared memory faces two main challenges: the higher number of valid execution behaviors and the larger coherence protocol's state space. This dissertation faces those challenges and targets an important design automation phase: the (pre-silicon) functional verification of the shared memory subsystem of a multicore chip, whose behavior is specified by a memory consistency model (MCM). The main scientific contribution is a novel approach to the building of MCM checkers, along with technical contributions on random test generation and directed test generation. The contributions were reported by two papers in a premier IEEE/ACM conference and two articles in the most prestigious IEEE journal on Computer Aided Design of Integrated Circuits and Systems.

Palavras-chave: Verification, Multicore, Shared memory, Random test generation, Consistency, Coherence, Store atomicity

Referências

Andrade, G. A. G., Graf, M., and dos Santos, L. C. V. (2020a). Chaining and Biasing: Test Generation Techniques for Shared-Memory Verification. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 39(3):728–741.

Andrade, G. A. G., Graf, M., Pfeifer, N., and dos Santos, L. C. V. (2018). Steep Coverage-ascent Directed Test Generation for Shared-memory Verification of Multicore Chips. In 2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Andrade, G. A. G., Graf, M., Pfeifer, N., and dos Santos, L. C. V. (2020b). A Directed Test Generator for Shared-Memory Verification of Multicore Chip Designs. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 39(12):5295–5303.

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