Timing Optimization During the Physical Synthesis of Cell-Based VLSI Circuits
Resumo
The evolution of CMOS technology made possible integrated circuits with billions of transistors assembled into a single silicon chip, giving rise to the jargon Very-Large-Scale Integration (VLSI). VLSI circuits span a wide range class of applications, including Application Specific Circuits and Systems-On-Chip. The latter are responsible for fueling the consumer electronics market, especially in the segment of smartphones and tablets, which are responsible for pushing hardware performance requirements every new generation. The required clock frequency affects the performance of a VLSI circuit and induces timing constraints that must be properly handled by synthesis tools. This thesis focuses on techniques for timing closure of cellbased VLSI circuits, i.e. techniques able to iteratively reduce the number of timing violations until the synthesis of the synchronous digital system reaches the specified target frequency.
Referências
Alpert, C. J., Mehta, D. P., and Sapatnekar, S. S. (2008). Handbook of algorithms for physical design automation. CRC Press.
Guth, C., Livramento, V., Netto, R., Fonseca, R., Güntzel, J. L., and Santos, L. (2015). Timing-driven placement based on dynamic net-weighting for efficient slack histogram compression. In ACM International Symposium on Physical Design, pages 141–148. (Best Paper Candidate).
Kahng, A. B., Lienig, J., Markov, I. L., and Hu, J. (2011). Vlsi physical design: From graph partitioning to timing closure. page 310. Springer.
Kim, M.-C., Hu, J., Li, J., and Viswanathan, N. (2015). Iccad-2015 cad contest in incremental timing-driven placement and benchmark suite. In IEEE/ACM International Conference on Computer-Aided Design, pages 921–926.
Liu, D., Yu, B., Chowdhury, S., and Pan, D. Z. (2016). Incremental layer assignment for critical path timing. In Design Automation Conference, pages 85:1–85:6. ACM.
Livramento, V., Guth, C., Netto, R., Güntzel, J. L., and dos Santos, L. C. (2015). Exploiting non-critical steiner tree branches for post-placement timing optimization. In IEEE/ACM International Conference on Computer-Aided Design, pages 528–535.
Livramento, V., Liu, D., Chowdhury, S., Yu, B., Xu, X., Pan, D. Z., Guntzel, J. L., and dos Santos, L. C. (2016a). Incremental layer assignment driven by an external signoff timing engine. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
Livramento, V., Netto, R., Guth, C., Güntzel, J. L., and Dos Santos, L. C. (2016b). Clock-tree-aware incremental timing-driven placement. ACM Transactions on Design Automation of Electronic Systems, 21(3):38.
Livramento, V. S., Guth, C., Güntzel, J. L., and Johann, M. O. (2014). A hybrid technique for discrete gate sizing based on lagrangian relaxation. ACM Transactions on Design Automation of Electronic Systems, 19(4):40.
Netto, R., Guth, C., Livramento, V., Castro, M., Pilla, L. L., and Güntzel, J. L. (2016a). Exploiting parallelism to speed up circuit legalization. In IEEE International Conference on Electronics, Circuits and Systems, pages 624–627.
Netto, R., Livramento, V., Guth, C., dos Santos, L. C., and Güntzel, J. L. (2016b). Evaluating the impact of circuit legalization on incremental optimization techniques. In IEEE Symposium on Integrated Circuits and Systems Design, pages 1–6.
Netto, R., Livramento, V., Guth, C., dos Santos, L. C., and Guntzel, J. L. (2016c). Speeding up incremental legalization with fast queries to multidimensional trees. In IEEE Computer Society Annual Symposium on VLSI, pages 36–41.
Yu, B., Liu, D., Chowdhury, S., and Pan, D. Z. (2015). TILA: Timing-driven incremental layer assignment. In IEEE/ACM International Conference on Computer-Aided Design, pages 110–117.
