Resource Tuning in a Multipath Superscalar Architecture

  • Tatiana G. S. dos Santos UFRGS
  • Maurício L. Pila UFRGS
  • Rafael R. dos Santos UNISC
  • Eliseu Monteiro Chaves Filho UFRJ
  • Sérgio Bampi UFRGS
  • Philippe O. A. Navaux UFRGS
  • Mario D. Nemirovsky University of California at Santa Cruz

Resumo


This paper presents the resource tuning in a multipath superscalar architecture model. The main goal of this model is to provide a high bandwidth for superscalar architectures that need a high instruction throughput. This architecture has an aggressive fetch mechanism to increase the number of instructions available to the execution stage of the pipeline, allowing a high number of instructions to be executed per cycle. To achieve this, instructions from multiple paths are fetched in the same clock cycle. The model results in a reduction of the occurrence of breaks in the flow. A more detailed study into the resource distribution throughout the architecture is needed. Simply increasing the number of resources to support throughput is not recommended, given the prohibitive implementation costs. The resource tuning of this superscalar architecture is then an important focus of research, to balance resource requirements and to tune them.

Palavras-chave: Resource Tuning, Superscalar Architectures, Multipath Fetch Mechanism

Referências

CHAVES FILHO, Eliseu Monteiro. Arquiteturas Super Escalares: Efeito de Alguns Parâmetros sobre o Desempenho. Rio de Janeiro: COPPE/UFRJ, 1994. PhD thesis.

CHAVES FILHO, Eliseu M.; FERNANDES, Edil S. T. On the Performance of Superscalar Architectures. Journal of the Brazilian Computer Society. Rio de Janeiro, v.2, n. 1, p. 38-50, Jul. 1995.

EGGERS, Susan J. et al. Simultaneous Multithreading: A Plataform for Next-Generation Processors.

HENNESSY, John: PATTERSON David. Computer Architecture: A Quantitative Approach. San Francisco: Morgan Kaufmann Publishers, segunda edição, 1996.

Mulflux: Superscalar Architectures with Multiple Instruction Flows, Research Proposal submitted to the Brazilian National Research Council, 1995.

The MULFLUX Project, Second Evaluation Report, May 1999.

PEIR, Jih-Know: HSU, Windsor W.; SMITH, Alan J. Implementations Issues in Modern Cache Memory Technical Report. November 18, 1998. CSD-98-1023: Computer Science Departament. Berkeley University.

ROTEMBERG. Eric; BENNET, Steve: SMITH, Jim Trace Cache: a Low Latency Approach to High Bandwidth Instruction Fetching. Madison: University of Wisconsin-Madison/Computer Science Departament, 1996. Technical Report.

SANTOS, Rafael R.; NAVAUX, Philippe O. A. Mecanismo de Busca Especulativa de Múltiplos Fluxos de Instruções. Porto Alegre: PPGCC/UFRGS. 1997. Master thesis.

SANTOS, Rafael R.; NAVAUX, Philippe O. A. Analysing a Multiflowed Superscalar Speculative Instruction Fetch Mechanism. In: EUROPAR. Southampton, October 1998. Proceedings.... Lecture Notes in Computer Science, 1998.

SMITH, James E.; VAJAPEYAM, Sriram. Trace Processors: Moving to Fourth-Generation. Computer, Los Alamitos. v.30, n.9, p.68-74, Sep. 1997.

SOHI, G. S.; BREACH. S. E.: VJJAYKUMAR. T. N. Multiscalar Processors. Computer Architecture News, New York, v.23, n.2, p. 414-425, 1995.

TOMASULO, R. M. An Efficient Algorithm for Exploiting Multiple Arithmetic Units. IBM Journal of Research and Development. Armonk, v. , n. , p. 25-33, Jan. 1967.

THORNTON, James E. Parallel Operation in the Control Data 6600. In: AFIPS Fali Joint Computer Conference, 1964. v.26. pt. 2, pp. 30-40.

WALLACE, Steven O. Performance Analisys of a Superscalar Architecture, Irvine: University of California. 1993. PhD thesis

YEH, Tse-Yu: PATT, Vale N. Two-Level Adaptive Training Branch Prediction. In: ANNUAL INTERNATIONAL SYMPOSIUM ON MICROARCHITECTURE. 24., 1991. Proceedings... New York: ACM, 1991. p. 51-61.
Publicado
29/09/1999
SANTOS, Tatiana G. S. dos; PILA, Maurício L.; SANTOS, Rafael R. dos; CHAVES FILHO, Eliseu Monteiro; BAMPI, Sérgio; NAVAUX, Philippe O. A.; NEMIROVSKY, Mario D.. Resource Tuning in a Multipath Superscalar Architecture. In: INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE AND HIGH PERFORMANCE COMPUTING (SBAC-PAD), 11. , 1999, Natal. Anais [...]. Porto Alegre: Sociedade Brasileira de Computação, 1999 . p. 27-34. DOI: https://doi.org/10.5753/sbac-pad.1999.19768.