Volume Rendering FPGA Hardware

  • J. Hesser Universität Mannheim
  • A. Kugel Universität Mannheim
  • H. Singpiel Universität Mannheim
  • B. Vettermann Universität Mannheim
  • R. Männer Universität Mannheim

Resumo


This paper discusses the implementation of volume rendering on FPGA hardware. The FPGA board is based on a 2x2 matrix of FPGA devices that are reprogrammed for different data processing tasks that occur during rendering. Moreover, it is shown how branch and data hazards are overcome in the pipelined system by multithreading.

Palavras-chave: FPGA, PCI, Volume Rendering, Visualization, Reconfigurable Computing

Referências

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A. Kugel, H, Singpiel, J Hesser., R. Männer. ATLANTIS: A hybrid approach combining the power of FPGA and RISC processor based on CompactPCI in Proc. FPGA '99, Monterey, CA, 1999.
Publicado
29/09/1999
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HESSER, J.; KUGEL, A.; SINGPIEL, H.; VETTERMANN, B.; MÄNNER, R.. Volume Rendering FPGA Hardware. In: INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE AND HIGH PERFORMANCE COMPUTING (SBAC-PAD), 11. , 1999, Natal. Anais [...]. Porto Alegre: Sociedade Brasileira de Computação, 1999 . p. 265-270. DOI: https://doi.org/10.5753/sbac-pad.1999.19799.