The Performance of Cache Coherency in SCI-based Multiprocessors

  • Roberto A. Hexsel UFPR
  • Nigel P. Topham University of Edinburgh

Resumo


The Scalable Coherent Interface (SCI) is an IEEE/ANSI standard that defines a hardware platform for scalable shared-memory multiprocessors. This paper contains a quantitative performance evaluation of SCI-connected multiprocessors that assesses both the communication and cache coherence subsystems. 1D, 2D and 3D tori with 16 and 64 nodes are investigated. For the architecture (100MHz Sparc, 2 levels of caches) and workload simulated, it was found that raw network bandwidth seen by a processing element is under 100Mbytes/s. The 3-D toros is 10-15% faster than the 2-D toros for programs that generate high leveis of network traffic. Otherwise, the differences in performance between 2-D and 3-D tori are negligible.

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Publicado
04/08/1996
HEXSEL, Roberto A.; TOPHAM, Nigel P.. The Performance of Cache Coherency in SCI-based Multiprocessors. In: INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE AND HIGH PERFORMANCE COMPUTING (SBAC-PAD), 8. , 1996, Recife. Anais [...]. Porto Alegre: Sociedade Brasileira de Computação, 1996 . p. 47-56. DOI: https://doi.org/10.5753/sbac-pad.1996.19813.