Extração do Paralelismo em Arquiteturas com Capacidade de Execução Condicional
Resumo
O artigo apresenta o modelo CONDEX: uma arquitetura do tipo VLIW com capacidade de execução condicional. A arquitetura básica é formada por múltiplas unidades funcionais independentes que podem operar concorrentemente, processando diversas instruções procedendo do mesmo programa de aplicação. Além da especificação do modelo de arquitetura, o artigo descreve algumas técnicas para geração de código paralelo para configurações derivadas do modelo CONDEX e os experimentos para avaliar a qualidade desse código.
Referências
R. D. Acosta, J. Kjelstrup, and H. C. Torng, "An Instruction Issuing Approach to Enhancing Performance in Multiple Functional Unit Processors," IEEE Transactions on Computers, Vol. 35, No. 9, September 1986, pp. 815828.
Augustus K. Uht, "Hardware Extraction of Low Level Cocurrency from Sequential instruction Streams," Ph.D. Thesis, Carnegie-Mellon University, December 1985.
R. P. Colwell, R. P. Nix, J. J. O' Donnell, D. B. Papworth and P. K. Rodman, "A VLIW Architecture for a Trace Scheduling Compiler," IEEE Transactions on Computers, Vol. 37, No. 8, August 1988, pp. 967979.
S. D. Conte, "Elementary Numerical Analysis," McGraw-Hill Book Co., New York, NY, USA, 1965.
David R. Ditzel, e Hubert R Mclellan, "Branch Folding in the CRISP Microprocessor: Reducing Branch Delay to Zero," Proceedings of the 14th Annual international Symposium on Computer Architecture, 1987, pp. 2-9. John R. Ellis, "Bulldog: A Compiler for VLIW Architectures," ACM Doctoral Dissertation Award 1985, The MIT Press, USA, 1986.
Edil S. T. Fernandes e Anna Dolejsi Santos, "Arquiteturas Super Escalares: Detecção e Exploração do Paralelismo de Baixo Nível," VIII Escola de Computação, 1992.
Edil S. T. Fernandes, Anna Dolejsi Santos and Claudio L. de Amorim, "Conditional Execution: an Approach for Eliminating the Basic Block Barriers," Microprocessing and Microprogramming The Euromicro Journal, North Holland, Vol. 40, Numbers 1012, December 1994, pp. 689-692.
Joseph A. Fisher, "Trace Scheduling: A Technique for Global Microcode Compaction," IEEE Transactions on Computers, Vol. C-30, No. 7, July 1981, pp. 478-490.
J oseph A. Fisher, "VLIW Machine: A Multiprocessor for Compiling Scientific Code," Computer, July 1984, pp. 45-53.
S. Gray and R. Adams, "Using Conditional Execution to Exploit lnstruction Level Concurrency," Technical Report no. 181, School of Information Sciences, Division of Computer Science, University of Hertfordshire, March 1994.
M. Johnson, "Superscalar Microprocessor Design," Prentice Hall, 1991.
R. M. Keller, "Look-Ahead Processors," Computing Surveys, Vol. 7, No. 4, December 1975; pp. 177195.
David Landskov, Scott Davidson, Bruce Shriver, and Patrick W. Mallet, "Local Microcode Compaction Techniques," Computing Surveys, Vol. 12, No. 3, September 1980, pp. 261-294.
F. H. McMahon, "Fortran Kernels: MFLOPS," Lawrence Livermore National Laboratory,1983.
A. Nicolau, "Percolation Scheduling: A Parallel Compilation Technique," Technical Report TR-85-678, Department of Computer Science, Cornell University, May 1985.
A. Nicolau and R. Potasman, "Realistic Scheduling: Compaction for Pipelined Architectures," Proceedings of the 23rd Annual International Workshop on Microprogramming and Microarchitecture MICRO-23, ACM and IEEE Computer Society, November 1990, pp. 69-79.
D. N. Pnevmatikatos and G. S. Sohi, "Guarded Execution and Branch Prediction in Dynamic ILP Processors," Proceedings of the 21st Annual International Symposium on Computer Architecture, 1994, pp. 120-129.
Anna Dolejsi Santos, "Efeito da Execução Condicional em Arquiteturas Paralelas," Tese de Doutorado, CO PPE/UFRJ, Programa de Engenharia de Sistemas e Computação, 1994.
F. L. Steven, G. B. Steven and L. Wang, "An Evaluation of the iHARP Multiple Instruction Issue Processor," Euromicro 94, September,1994.
Daniel Tabak, "Advanced Microprocessors," Me Graw-Hill, Inc., USA, 1991.
M. Tokoro, T. Takizuka, E. Tamura, and I. Yamaura, "A Technique of Global Optimization of Microprograms," Proceedings of the 11th Annual Microprogramming Workshop, 1978, pp. 4150.
N. Wirth, "Algorithms + Data Structures = Programs," Prentice-Hall, Inc., 1976.
Augustus K. Uht, "Hardware Extraction of Low Level Cocurrency from Sequential instruction Streams," Ph.D. Thesis, Carnegie-Mellon University, December 1985.
R. P. Colwell, R. P. Nix, J. J. O' Donnell, D. B. Papworth and P. K. Rodman, "A VLIW Architecture for a Trace Scheduling Compiler," IEEE Transactions on Computers, Vol. 37, No. 8, August 1988, pp. 967979.
S. D. Conte, "Elementary Numerical Analysis," McGraw-Hill Book Co., New York, NY, USA, 1965.
David R. Ditzel, e Hubert R Mclellan, "Branch Folding in the CRISP Microprocessor: Reducing Branch Delay to Zero," Proceedings of the 14th Annual international Symposium on Computer Architecture, 1987, pp. 2-9. John R. Ellis, "Bulldog: A Compiler for VLIW Architectures," ACM Doctoral Dissertation Award 1985, The MIT Press, USA, 1986.
Edil S. T. Fernandes e Anna Dolejsi Santos, "Arquiteturas Super Escalares: Detecção e Exploração do Paralelismo de Baixo Nível," VIII Escola de Computação, 1992.
Edil S. T. Fernandes, Anna Dolejsi Santos and Claudio L. de Amorim, "Conditional Execution: an Approach for Eliminating the Basic Block Barriers," Microprocessing and Microprogramming The Euromicro Journal, North Holland, Vol. 40, Numbers 1012, December 1994, pp. 689-692.
Joseph A. Fisher, "Trace Scheduling: A Technique for Global Microcode Compaction," IEEE Transactions on Computers, Vol. C-30, No. 7, July 1981, pp. 478-490.
J oseph A. Fisher, "VLIW Machine: A Multiprocessor for Compiling Scientific Code," Computer, July 1984, pp. 45-53.
S. Gray and R. Adams, "Using Conditional Execution to Exploit lnstruction Level Concurrency," Technical Report no. 181, School of Information Sciences, Division of Computer Science, University of Hertfordshire, March 1994.
M. Johnson, "Superscalar Microprocessor Design," Prentice Hall, 1991.
R. M. Keller, "Look-Ahead Processors," Computing Surveys, Vol. 7, No. 4, December 1975; pp. 177195.
David Landskov, Scott Davidson, Bruce Shriver, and Patrick W. Mallet, "Local Microcode Compaction Techniques," Computing Surveys, Vol. 12, No. 3, September 1980, pp. 261-294.
F. H. McMahon, "Fortran Kernels: MFLOPS," Lawrence Livermore National Laboratory,1983.
A. Nicolau, "Percolation Scheduling: A Parallel Compilation Technique," Technical Report TR-85-678, Department of Computer Science, Cornell University, May 1985.
A. Nicolau and R. Potasman, "Realistic Scheduling: Compaction for Pipelined Architectures," Proceedings of the 23rd Annual International Workshop on Microprogramming and Microarchitecture MICRO-23, ACM and IEEE Computer Society, November 1990, pp. 69-79.
D. N. Pnevmatikatos and G. S. Sohi, "Guarded Execution and Branch Prediction in Dynamic ILP Processors," Proceedings of the 21st Annual International Symposium on Computer Architecture, 1994, pp. 120-129.
Anna Dolejsi Santos, "Efeito da Execução Condicional em Arquiteturas Paralelas," Tese de Doutorado, CO PPE/UFRJ, Programa de Engenharia de Sistemas e Computação, 1994.
F. L. Steven, G. B. Steven and L. Wang, "An Evaluation of the iHARP Multiple Instruction Issue Processor," Euromicro 94, September,1994.
Daniel Tabak, "Advanced Microprocessors," Me Graw-Hill, Inc., USA, 1991.
M. Tokoro, T. Takizuka, E. Tamura, and I. Yamaura, "A Technique of Global Optimization of Microprograms," Proceedings of the 11th Annual Microprogramming Workshop, 1978, pp. 4150.
N. Wirth, "Algorithms + Data Structures = Programs," Prentice-Hall, Inc., 1976.
Publicado
29/07/1995
Como Citar
SANTOS, Anna Dolejsi; FERNANDES, Edil S. T..
Extração do Paralelismo em Arquiteturas com Capacidade de Execução Condicional. In: INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE AND HIGH PERFORMANCE COMPUTING (SBAC-PAD), 7. , 1995, Canela.
Anais [...].
Porto Alegre: Sociedade Brasileira de Computação,
1995
.
p. 77-91.
DOI: https://doi.org/10.5753/sbac-pad.1995.19855.
