Sistema Gerador de Geradores de Código para Arquiteturas Superescalares
Resumo
Para obter um bom desempenho nas arquiteturas RISC, em particular, as arquiteturas superescalares, é necessário haver um bom relacionamento entre as tecnologias dos compiladores e as arquiteturas dos processadores. Baseado neste fato, arquiteturas recentes de computadores motivam pesquisas por técnicas de implementação de compiladores mais eficientes. Isto, contudo, acarreta maior complexidade dos compiladores porque estes novos computadores alcançam a eficiência, delegando aos compiladores a solução de problemas complexos de geração e otimização de código. Mostramos neste trabalho o projeto de um sistema gerador de geradores de código apropriado para arquiteturas superescalares. Mostramos também resultados de um estudo sobre vários problemas relacionados com a geração de código para estes processadores.
Referências
Benitez, Manuel E. and Davidson, Jack W., A Portable Global Optimizer and Linker, ACM Sigplan Notices, 23, 7, July/1988.
Bradlee, David G. et al., The Marion System for Retargetable Instruction Scheduling, ACM Sigplan Conference on Programming Language Design and Implementation, ACM Sigplan Notices 26(7), July/1991.
Bradlee, David G. et al., Integrating Register Allocation and Instruction Scheduling for RISCs, ASPLOS-IV Proceedings Fourth International Conference on Architectural Support for Programming Languages and Operating Systems, Santa Clara, California, April/1991.
Bigonha, Mariza A. Silva, Otimização de Código em Máquina Superescalares, Tese de Doutorado, 01-PUC/RJ, Abril/1994.
Bigonha, Mariza A. S. and Rangel, Jos Lucas M., Linguagens para Descrição de Arquiteturas de Computadores, VI SBAC - Simpósio Brasileiro de Arquitetura de Computadores e Processamento de Auto Desempenho, Caxambu, MG, 137-153, Agosto/1994.
Bigonha, Roberto S., SC'RTPT An Object Oriented Language for Denotational Semantics (User's Manual and Reference}, DCC UFMG, RT 03/94.
Chaitin, Gregory J., Register Allocation and spilling via graph coloring, ACM Sigplan Notices, 17, 6, ACM Sigplan Symposium on Compiler Construction, June/1982.
Costa, Paulo S. S., Um Gerador Automático de Geradores de Código, Tese de Mestrado, PUC-RJ, Fevereiro/1990.
Davidson, Jack W., Simplifying Code Generction Through Peephole Optimization, DCSc The University of Arizona, Tucson Arizona, December/1981.
Fisher, Joseph A. et al., Parallel Processing: A smart compiler and a dump machine, ACM Sigplan Notices, 19, 6, Proceedings of the ACM Sigplan, Symposium on Compiler Construction, June/1984,
Fisher, Joseph A., Trace Scheduling: A Technique for Global Microcode Compactation, IEEE Transactions on Computers, 30, 7, July/1981.
Fraser, Christopher W. and Hanson, David R., A Code Generation Interface for ANSI C, DCS, Princeton University, Research Report, CS-TR-270-90, Last Revised September 1992.
Gibbons, Phillip B. and and Muchnick, Steven S., Efficient Instruction Scheduling for a Pipelined Architecture, Proceedings of the ACM Sigplan'86 Symposium on Compiler Construction, ACM Sigplan Notices 21(7), July/1986.
Goodman, James R. and Wei-Chung-Hsu, Code Scheduling and Register Allocation in Large Basic Blocks, International Conference on Supercomputing Conference ACM-PRESS Proceedings, St. Maio France, July/1988.
Hennessy, John and Gross, Thomas, Code Generation and Reorganization in the Prefence of Pipeline Constraints, Conference Record of the 9th Annual ACM Symposium on Principies of Programming Languages, 128-133, Albuquerque New Mexico, January/1982.
Hennessy, John and Gross, Thomas, Postpass Code Optimization of Pipeline Constraints, ACM Transactions on Programming Languages, 1983, 5(3).
Henry, Robert R., Code Generation by Table Lookup, Computer Science Department, University of Washington, Technical Report, 87-07-07, FR-35 Seattle, WA 89195 USA, July/ 1987.
Intel, Inc., i860 64-bit Microprocessor Programmer's Reference Manual Intel, Inc., Santa Clara, California.,1989.
Kems, Daniel R., Balanced Scheduling: Instruction Scheduling when Memory Latency is Uncertain, Proceedings of the ACM Sigplan'93 Conference on Programming Language Design and Implementation, Albuquerque NM, ACM Sigplan Notices Vol. 28 number 6 june-1993.
Motorola., Inc., MC88100 RISC Microprocessor User's Manual, Prentice-Hall, Englewood Cliffs, second edition, New Jersey/ 1990.
Motorola., Inc., MC68020 32-Bit Microprocessor User's Manual Prentice-Hall, Englewood Cliffs, New Jersey/1984.
Muchnick, Steven and others, Optimizing Compilers for the SPARC Architecture An Overview, IEEE Computer Society Intemational Conference, 284-288, SPRING COMPCON, (33), 1988.
Pinter, Shlomit S., Regiater Allocation with Instruction Scheduling: a New Approach, Proceedings of the ACM Sigplan'93 Conference on Programming Language Design and Implementation, Albuquerque NM, June/1993, ACM Sigplan Notices Vol. 28 number 6 june-1993.
Stallman, Richard M., Using and Porting GNU C, Free Software Foundation Incorporation, Cambridge Massa.chusetts, 1989
Souza, G. B., Técnicas de Otimização de Código para Arquiteturas RISC, Tese de Mestrado, DCC UNICAMP Campinas, 1992.
Tiemann, Michael D., The GNU lnstruction Scheduler, Stanford University, Class Report, CS 343, June/1989.
Warren Jr, H. S., Instruction Scheduling for the IBM RISC System/6000 Processor, Journal of Research and Development, 34, 1, January/1990.
Bradlee, David G. et al., The Marion System for Retargetable Instruction Scheduling, ACM Sigplan Conference on Programming Language Design and Implementation, ACM Sigplan Notices 26(7), July/1991.
Bradlee, David G. et al., Integrating Register Allocation and Instruction Scheduling for RISCs, ASPLOS-IV Proceedings Fourth International Conference on Architectural Support for Programming Languages and Operating Systems, Santa Clara, California, April/1991.
Bigonha, Mariza A. Silva, Otimização de Código em Máquina Superescalares, Tese de Doutorado, 01-PUC/RJ, Abril/1994.
Bigonha, Mariza A. S. and Rangel, Jos Lucas M., Linguagens para Descrição de Arquiteturas de Computadores, VI SBAC - Simpósio Brasileiro de Arquitetura de Computadores e Processamento de Auto Desempenho, Caxambu, MG, 137-153, Agosto/1994.
Bigonha, Roberto S., SC'RTPT An Object Oriented Language for Denotational Semantics (User's Manual and Reference}, DCC UFMG, RT 03/94.
Chaitin, Gregory J., Register Allocation and spilling via graph coloring, ACM Sigplan Notices, 17, 6, ACM Sigplan Symposium on Compiler Construction, June/1982.
Costa, Paulo S. S., Um Gerador Automático de Geradores de Código, Tese de Mestrado, PUC-RJ, Fevereiro/1990.
Davidson, Jack W., Simplifying Code Generction Through Peephole Optimization, DCSc The University of Arizona, Tucson Arizona, December/1981.
Fisher, Joseph A. et al., Parallel Processing: A smart compiler and a dump machine, ACM Sigplan Notices, 19, 6, Proceedings of the ACM Sigplan, Symposium on Compiler Construction, June/1984,
Fisher, Joseph A., Trace Scheduling: A Technique for Global Microcode Compactation, IEEE Transactions on Computers, 30, 7, July/1981.
Fraser, Christopher W. and Hanson, David R., A Code Generation Interface for ANSI C, DCS, Princeton University, Research Report, CS-TR-270-90, Last Revised September 1992.
Gibbons, Phillip B. and and Muchnick, Steven S., Efficient Instruction Scheduling for a Pipelined Architecture, Proceedings of the ACM Sigplan'86 Symposium on Compiler Construction, ACM Sigplan Notices 21(7), July/1986.
Goodman, James R. and Wei-Chung-Hsu, Code Scheduling and Register Allocation in Large Basic Blocks, International Conference on Supercomputing Conference ACM-PRESS Proceedings, St. Maio France, July/1988.
Hennessy, John and Gross, Thomas, Code Generation and Reorganization in the Prefence of Pipeline Constraints, Conference Record of the 9th Annual ACM Symposium on Principies of Programming Languages, 128-133, Albuquerque New Mexico, January/1982.
Hennessy, John and Gross, Thomas, Postpass Code Optimization of Pipeline Constraints, ACM Transactions on Programming Languages, 1983, 5(3).
Henry, Robert R., Code Generation by Table Lookup, Computer Science Department, University of Washington, Technical Report, 87-07-07, FR-35 Seattle, WA 89195 USA, July/ 1987.
Intel, Inc., i860 64-bit Microprocessor Programmer's Reference Manual Intel, Inc., Santa Clara, California.,1989.
Kems, Daniel R., Balanced Scheduling: Instruction Scheduling when Memory Latency is Uncertain, Proceedings of the ACM Sigplan'93 Conference on Programming Language Design and Implementation, Albuquerque NM, ACM Sigplan Notices Vol. 28 number 6 june-1993.
Motorola., Inc., MC88100 RISC Microprocessor User's Manual, Prentice-Hall, Englewood Cliffs, second edition, New Jersey/ 1990.
Motorola., Inc., MC68020 32-Bit Microprocessor User's Manual Prentice-Hall, Englewood Cliffs, New Jersey/1984.
Muchnick, Steven and others, Optimizing Compilers for the SPARC Architecture An Overview, IEEE Computer Society Intemational Conference, 284-288, SPRING COMPCON, (33), 1988.
Pinter, Shlomit S., Regiater Allocation with Instruction Scheduling: a New Approach, Proceedings of the ACM Sigplan'93 Conference on Programming Language Design and Implementation, Albuquerque NM, June/1993, ACM Sigplan Notices Vol. 28 number 6 june-1993.
Stallman, Richard M., Using and Porting GNU C, Free Software Foundation Incorporation, Cambridge Massa.chusetts, 1989
Souza, G. B., Técnicas de Otimização de Código para Arquiteturas RISC, Tese de Mestrado, DCC UNICAMP Campinas, 1992.
Tiemann, Michael D., The GNU lnstruction Scheduler, Stanford University, Class Report, CS 343, June/1989.
Warren Jr, H. S., Instruction Scheduling for the IBM RISC System/6000 Processor, Journal of Research and Development, 34, 1, January/1990.
Publicado
29/07/1995
Como Citar
BIGONHA, Mariza Andrade da Silva; NETTO, José Lucas Mourão Rangel.
Sistema Gerador de Geradores de Código para Arquiteturas Superescalares. In: INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE AND HIGH PERFORMANCE COMPUTING (SBAC-PAD), 7. , 1995, Canela.
Anais [...].
Porto Alegre: Sociedade Brasileira de Computação,
1995
.
p. 287-302.
DOI: https://doi.org/10.5753/sbac-pad.1995.19869.
