Protocolo “Snoopy” adaptativo para um Sistema Multiprocessador Baseado em Hierarquia de Barramentos
Resumo
Este trabalho apresenta e descreve um protocolo adaptativo de coerência de cache baseado nos esquemas "snoopy" para um sistema multiprocessador de memória compartilhada baseado na hierarquia de barramentos. O protocolo permite diminuir o tráfego adicional na rede produzido pelas ações de coerência e se adapta dinamicamente ao compartilhamento e aos padrões de referência que variam amplamente para os diferentes programas aplicativos. A sua avaliação de desempenho é feita com uma análise comparativa com os protocolos Dash e SCI (baseados em esquemas diretórios).
Referências
ANDERSON, C.; BAER, J .L. A Multi-Level Hierarchical Cache Coherence Protocol for Multiprocessors. Technical Report, University of Washintong, 1992
GOLDSCHMIDT, S.R. Simulation of Multiprocessors: Accuracy and Performance. PhD. Thesis, IEEE, University of Stanford, Jun. 1993.
GOODMAN, J.R.; WOEST, P.J. The Wisconsin Multicube: A New Large Scale cache Coherent Multiprocessor. In: Ann. Int. Symp. on Computer Architecture, IEEE, 15th. Proceedings, p. 422-31, 1988.
GUSTAVSON, D.B. The Scalable Coherent Interface and Related Standards Projects. IEEE Micro Cbips, Systems, Software and Applications, p. 10-22, Feb. 1992.
HERROD, S.A. Tango-Lite: A Multiprocessor Simulation Enviroment - lntroduction and User's Guide. Technical Report, Stanford University, Sep. 1993.
JOU, T.S.; ENBODY, R. A Scalable Snoopy Coherence Scheme on Distributed Shared-Memory Multiprocessors. In: IEEE Supercomputing. Proceedings, p. 652- 60, 1992.
LENOSKY, D. et al. The Directory-Based Cache Coherence Protocol for the DASH Multiprocessor. In: Ann. Symp. on Computer Architecture, IEEE, 17th. Proceedings, p. 148-59, 1990.
LENOSKY, D. et al. The Stanford DASH Multiprocessor. IEEE Computer, p. 63-79, Mar. 1992.
LENOSKY, D. et al. The DASH Prototype: Implementation and Performance. ACM Transactions on Computer Systems, p. 92-103, 1992.
PAPAMARCOS, M.; PATEL, J. A Low Overhead Coherence Solution for Multiprocessors with Private Cache Memories. In: Ann. lnt. Symp. on Computer Architecture, IEEE, 11th. Proceedings, p. 348-54, 1984.
P1596 Working Group, SCI (Scalable Coherent Interface) -Cache Coherence Overview. Technical Report Revision 0.33, IEEE Computer Society, Nov. 1989.
SINGH, J.P.;WEBER, W.D.; GUPTA, A. Splash: Stanford Parallel Applications for Shared Memory. Technical Report CSL-TR-91-469, Stanford University, Apr. 1991.
TVING, Ivan. Simulation Environment for Multiprocessor Cache Based Supercomputer using the Scalable Coherent Interface (SCI-IEEE-P1596) in a Ring-Based Topology. Master's Thesis, DTH ID-E 579, University of Denmark, p. 199, Feb. 1994.
WlLSON, A.W. Hierarchical cache/Bus Architecture for Shared Memory Multiprocessors. In: Ann. Int. Symp. on Computer Architecture, IEEE, 14th. Proceedings, p. 244-52, 1987.
WINSOR, D.C.; MUDGE, T.N. Analisys of Bus Hierarchies for Multiprocessors. In: Ann. lnt. Symp. on Computer Architecture, IEEE, 15th. Proceedings, p. 100-7, 1988.
GOLDSCHMIDT, S.R. Simulation of Multiprocessors: Accuracy and Performance. PhD. Thesis, IEEE, University of Stanford, Jun. 1993.
GOODMAN, J.R.; WOEST, P.J. The Wisconsin Multicube: A New Large Scale cache Coherent Multiprocessor. In: Ann. Int. Symp. on Computer Architecture, IEEE, 15th. Proceedings, p. 422-31, 1988.
GUSTAVSON, D.B. The Scalable Coherent Interface and Related Standards Projects. IEEE Micro Cbips, Systems, Software and Applications, p. 10-22, Feb. 1992.
HERROD, S.A. Tango-Lite: A Multiprocessor Simulation Enviroment - lntroduction and User's Guide. Technical Report, Stanford University, Sep. 1993.
JOU, T.S.; ENBODY, R. A Scalable Snoopy Coherence Scheme on Distributed Shared-Memory Multiprocessors. In: IEEE Supercomputing. Proceedings, p. 652- 60, 1992.
LENOSKY, D. et al. The Directory-Based Cache Coherence Protocol for the DASH Multiprocessor. In: Ann. Symp. on Computer Architecture, IEEE, 17th. Proceedings, p. 148-59, 1990.
LENOSKY, D. et al. The Stanford DASH Multiprocessor. IEEE Computer, p. 63-79, Mar. 1992.
LENOSKY, D. et al. The DASH Prototype: Implementation and Performance. ACM Transactions on Computer Systems, p. 92-103, 1992.
PAPAMARCOS, M.; PATEL, J. A Low Overhead Coherence Solution for Multiprocessors with Private Cache Memories. In: Ann. lnt. Symp. on Computer Architecture, IEEE, 11th. Proceedings, p. 348-54, 1984.
P1596 Working Group, SCI (Scalable Coherent Interface) -Cache Coherence Overview. Technical Report Revision 0.33, IEEE Computer Society, Nov. 1989.
SINGH, J.P.;WEBER, W.D.; GUPTA, A. Splash: Stanford Parallel Applications for Shared Memory. Technical Report CSL-TR-91-469, Stanford University, Apr. 1991.
TVING, Ivan. Simulation Environment for Multiprocessor Cache Based Supercomputer using the Scalable Coherent Interface (SCI-IEEE-P1596) in a Ring-Based Topology. Master's Thesis, DTH ID-E 579, University of Denmark, p. 199, Feb. 1994.
WlLSON, A.W. Hierarchical cache/Bus Architecture for Shared Memory Multiprocessors. In: Ann. Int. Symp. on Computer Architecture, IEEE, 14th. Proceedings, p. 244-52, 1987.
WINSOR, D.C.; MUDGE, T.N. Analisys of Bus Hierarchies for Multiprocessors. In: Ann. lnt. Symp. on Computer Architecture, IEEE, 15th. Proceedings, p. 100-7, 1988.
Publicado
01/08/1994
Como Citar
ORDOÑEZ, Edward D. M.; DELGADO, Martha X. T.; SANTOS, Celso A . S.; KOFUJI, Sergio T..
Protocolo “Snoopy” adaptativo para um Sistema Multiprocessador Baseado em Hierarquia de Barramentos. In: INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE AND HIGH PERFORMANCE COMPUTING (SBAC-PAD), 6. , 1994, Caxambu.
Anais [...].
Porto Alegre: Sociedade Brasileira de Computação,
1994
.
p. 171-181.
DOI: https://doi.org/10.5753/sbac-pad.1994.21884.
