Extending DLXsim for Parallel Architectures
Resumo
This paper presents two extensions of a RISC processor called DLX. We extend DLX's functionality for a vector and for a parallel architecture. The vector extension, DLXV, has pipelined vector functional units and is able to perform chained vector operations. The parallel extension, DLXMP, is a message-passing multicomputer with a basic DLX on each node. We present simulators for both extensions, describe their major features, and show examples of their use.
Palavras-chave:
RISC processor simulation, vector architectures, multicomputers, high-performance computing
Referências
Hennessy, J. L., AND Patterson, D. A. Computer Architecture: A Quantitative Approach. Morgan Kaufmann Publishers Inc., 1990.
Hostetter, L. B., and Mirtich, B. DLXsim — A Simulator for DLX. University of California, 1990.
Laz, C. G., AND Surra, J. E. A study of partitioned vector register files. In Supercomputing’ 92 (Minneapolis, November 1992), pp. 94-103.
Mrnpgs, C. L. Guidelines for Using DLXVsim and DLXMPrim. University of Ilinois at Urbana-Champaign, 1994.
STELLNER, G., BT AL. NXLIB User's Guide. Technische Universitat Minchen, 1993.
Hostetter, L. B., and Mirtich, B. DLXsim — A Simulator for DLX. University of California, 1990.
Laz, C. G., AND Surra, J. E. A study of partitioned vector register files. In Supercomputing’ 92 (Minneapolis, November 1992), pp. 94-103.
Mrnpgs, C. L. Guidelines for Using DLXVsim and DLXMPrim. University of Ilinois at Urbana-Champaign, 1994.
STELLNER, G., BT AL. NXLIB User's Guide. Technische Universitat Minchen, 1993.
Publicado
01/08/1994
Como Citar
MENDES, Celso L..
Extending DLXsim for Parallel Architectures. In: INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE AND HIGH PERFORMANCE COMPUTING (SBAC-PAD), 6. , 1994, Caxambu.
Anais [...].
Porto Alegre: Sociedade Brasileira de Computação,
1994
.
p. 243-258.
DOI: https://doi.org/10.5753/sbac-pad.1994.21889.
