Determinação dos Parâmetros Ideais de uma Arquitetura VLIW
Resumo
Máquinas VLIW (Very Long lnstruction Word machines) são arquiteturas paralelas que oferecem uma alternativa ao uso de Processadores Vetoriais e Multiprocessadores. Incorporando diversas unidades funcionais que podem operar em paralelo, essas máquinas podem ser caracterizadas pelas suas instruções, que incluem campos distintos para controlar diretamente cada um dos recursos do hardware subjacente. Esse trabalho descreve os experimentos que permitiram avaliar o efeito de importantes parâmetros arquiteturais no volume do paralelismo de baixo nível que pode ser extraido de programas de aplicação. Através da interpretação do código objeto de um processador comercial, derivado de uma bateria de programas de teste, determinou-se a configuração ideal da máquina VLIW capaz de atingir a taxa de aceleração máxima de cada programa de teste.
Referências
M. J. Flynn, "Very High-Speed Computing Systems", Proceedings of the IEEE 54, 1966, pp. 1901-1909.
J. A. Fisher, "Trace Scheduling: A Technique for Global Microcode Compaction", IEEE Transactions on Computers, Vol. C30, No. 7, July 1981, pp. 478-490.
D. D. Gagski and J. K. Peir, "Essential lssues in Multiprocessor Systems", Computer, Vol. 18, No. 6, June 1985, pp. 10-16.
J. A. Fisher, "The VLIW Machine: A Multiprocessor for Compiling Scientific Code", Computer, July 1984, pp. 174-182.
A. F. Souza, "Avaliando os Parâmetros de uma Arquitetura VLIW', Tese submetida ao corpo docente da COPPE/UFRJ, 1993.
R. P. Colwell, R. P. Nix, J. J. O'Donnell, D. B. Papworth and P. K. Rodman, "A VLIW Architecture for a Trace Scheduling Compile?, IEEE Transactions on Computers, Vol. 37, No. 8, August 1988, pp. 967-979.
A. Nicolau, "Percolation Scheduling: A Parallel Compilation Technique", Technical Report, Department of Computer Science, Cornell University, May 1985, TR 85-678.
D. Landskov, S. Davidson, and B. Shriver, "Local Microcode Compaction Techniques", Computer Surveys, Vol. 12, No. 3, September 1980, pp. 261-294.
S. Davidson, D. Landskov, B. D. Shriver and P W. Mallett, "Some Ezperiments in Local Microcode Compaction for Horizontal Machines", IEEE Transactions on Computers, Vol. C30, No. 7, July 1981, pp. 460-477.
A. Nicolau and J. A. Fisher, "Measuring the Parallelism Avaliable for Very Long lnstruction Word Architectures", IEEE Transactions on Computers, Vol. C33, No. 11, November 1984, pp. 968-976.
Arvind and V. Kathail, "A Multiple Processor Data Flow Machine that Supports Generalized Procedures", Proceedings of the 8th Annual Symposium on Computer Architecture, ACM (SIGARCH), vol. 9, No. 3, May 1981, pp. 291-302.
Intel, "i860 64-Bit Microprocessor Hardware Manual - Preliminary", Intel, Order Number: 240296-003, October 1989.
Intel, "i860 64-Bit Microprocessor Programmer's Reference Manual, Intel, 1989.
F. H. McMahon, "Fortran Kernels: MFLOPS', Lawrence Livermore National Laboratory, 1983.
Metaware, " HighC Programmer's Guide", Metaware Incorporated, Santa Cruz CA, 1990.
R. M. Tomasulo, "An Efficient Algorithm for Exploiting Multiple Arithmetic Units", IBM Journal, January 1967, pp. 25-33.
M. Tokoro, E. Tamura. and T. Takizuka., "Optimisation of Microprograms", IEEE Transactions on Computers, vol. C-30, No. 7, July 1981, pp. 491-504.
M. Harris, " Extending Microcode Compaction for Real Architectures", ACM Micro, No. 20, 1987, pp. 40-53.
S. U. Rao and A. K. Majumdar, "Global Microcode Compaction A Performance Evaluation by Simulation", Microprocessing and Microprogramming, North Holland, No. 20, 1988, pp. 159-174.
S. Da.sgupta. and J. Tartar, "The lndentification of Maximal Parallelism in Straight Line Microprograms", IEEE Transaction on Computers, vol. C-25, pp. 986-991, October, 1976.
A. V. Aho, R. Sethi and J. D. Ullman, "Compilers. Principies, Techniques, and Tools", Addison-Wesley, 1986.
J. A. Fisher, "Trace Scheduling: A Technique for Global Microcode Compaction", IEEE Transactions on Computers, Vol. C30, No. 7, July 1981, pp. 478-490.
D. D. Gagski and J. K. Peir, "Essential lssues in Multiprocessor Systems", Computer, Vol. 18, No. 6, June 1985, pp. 10-16.
J. A. Fisher, "The VLIW Machine: A Multiprocessor for Compiling Scientific Code", Computer, July 1984, pp. 174-182.
A. F. Souza, "Avaliando os Parâmetros de uma Arquitetura VLIW', Tese submetida ao corpo docente da COPPE/UFRJ, 1993.
R. P. Colwell, R. P. Nix, J. J. O'Donnell, D. B. Papworth and P. K. Rodman, "A VLIW Architecture for a Trace Scheduling Compile?, IEEE Transactions on Computers, Vol. 37, No. 8, August 1988, pp. 967-979.
A. Nicolau, "Percolation Scheduling: A Parallel Compilation Technique", Technical Report, Department of Computer Science, Cornell University, May 1985, TR 85-678.
D. Landskov, S. Davidson, and B. Shriver, "Local Microcode Compaction Techniques", Computer Surveys, Vol. 12, No. 3, September 1980, pp. 261-294.
S. Davidson, D. Landskov, B. D. Shriver and P W. Mallett, "Some Ezperiments in Local Microcode Compaction for Horizontal Machines", IEEE Transactions on Computers, Vol. C30, No. 7, July 1981, pp. 460-477.
A. Nicolau and J. A. Fisher, "Measuring the Parallelism Avaliable for Very Long lnstruction Word Architectures", IEEE Transactions on Computers, Vol. C33, No. 11, November 1984, pp. 968-976.
Arvind and V. Kathail, "A Multiple Processor Data Flow Machine that Supports Generalized Procedures", Proceedings of the 8th Annual Symposium on Computer Architecture, ACM (SIGARCH), vol. 9, No. 3, May 1981, pp. 291-302.
Intel, "i860 64-Bit Microprocessor Hardware Manual - Preliminary", Intel, Order Number: 240296-003, October 1989.
Intel, "i860 64-Bit Microprocessor Programmer's Reference Manual, Intel, 1989.
F. H. McMahon, "Fortran Kernels: MFLOPS', Lawrence Livermore National Laboratory, 1983.
Metaware, " HighC Programmer's Guide", Metaware Incorporated, Santa Cruz CA, 1990.
R. M. Tomasulo, "An Efficient Algorithm for Exploiting Multiple Arithmetic Units", IBM Journal, January 1967, pp. 25-33.
M. Tokoro, E. Tamura. and T. Takizuka., "Optimisation of Microprograms", IEEE Transactions on Computers, vol. C-30, No. 7, July 1981, pp. 491-504.
M. Harris, " Extending Microcode Compaction for Real Architectures", ACM Micro, No. 20, 1987, pp. 40-53.
S. U. Rao and A. K. Majumdar, "Global Microcode Compaction A Performance Evaluation by Simulation", Microprocessing and Microprogramming, North Holland, No. 20, 1988, pp. 159-174.
S. Da.sgupta. and J. Tartar, "The lndentification of Maximal Parallelism in Straight Line Microprograms", IEEE Transaction on Computers, vol. C-25, pp. 986-991, October, 1976.
A. V. Aho, R. Sethi and J. D. Ullman, "Compilers. Principies, Techniques, and Tools", Addison-Wesley, 1986.
Publicado
01/08/1994
Como Citar
SOUZA, Alberto Ferreira de; FERNANDES, Edil Severiano Tavares.
Determinação dos Parâmetros Ideais de uma Arquitetura VLIW. In: INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE AND HIGH PERFORMANCE COMPUTING (SBAC-PAD), 6. , 1994, Caxambu.
Anais [...].
Porto Alegre: Sociedade Brasileira de Computação,
1994
.
p. 297-316.
DOI: https://doi.org/10.5753/sbac-pad.1994.21893.
