SEMPRE: Uma Arquitetura SuperEscalar com Múltiplos Processos em Execução
Resumo
Este trabalho apresenta a arquitetura SEMPRE, projetada para executar múltiplos processos, ao invés de múltiplas threads, aproveitando assim a grande quantidade de processos existentes nas estações de trabalho compartilhadas e servidores de rede. Esta arquitetura emprega mecanismos inovadores que possibilitam a antecipação da troca de contexto entre processos, bem como a rápida remoção de instruções inconvenientes. Além disso, ela provê facilidades para o sistema operacional gerenciar processos com mínimo esforço.
Palavras-chave:
superescalar, multi-threading, gerenciamento de processos
Referências
Anderson. D. & Shanley. T., Pentium Processor System Architecture. MindShare. Inc., Addison-Wesley. Massachusetts, 433p. February. 1995.
Butler. M., et all. Single Instruction Stream Parallelism ls Greater Than Two. Proceedings of the 18th Annual lnternational Symposium on Computer Architecture. Toronto, Canada, May. 1991.
Chakravarty, D. & Cannon. C., PowerPC: Concepts, Architecture, and Design, J. Ranade Workstations Series. McGraw-Hill. USA, Inc., p.363. 1994.
Govindarajan. R. & Nemawarkar. S. S., SMALL: A Scalable Multithreaded Architecture to Exploit Large Locality. Proceedings of the Fourth IEEE Symposium on Parallel and Distributed Processing. Dallas, TX, Dec, 1992.
Hirata, H. et all, An Elementary Processor Architecture with Simultaneous Instruction Issuing from Multiple Threads, Proceedings of the 19th Annual International Symposium on Computer Architecture. ACM & IEEE-CS. 1992.
Jouppi, N. P. & Wall. D. W., Available lnstruction-Level Parallelism for Superscalar and Superpipelined Machines, Research Report, Digital, Westem Research Laboratory, Palo Alto, California, July, 1989.
Laudon, J., et all, lnterleaving: A Multithreading Technique Targeting Multiprocessors and Workstations, Proceedings of the lnternational Conference on ASPLOS. Oct. 1994.
Lipasti. M.H. & Shen, J.P., Exceeding the Dataflow Limit via Value Prediction. 29th Micro, Paris, France, December, 1996.
MIPS R10000 Microprocessor User's Manual, Version 1.0, MIPS Technologies, Inc. North Shoreline, Mountain View, California, June, 1995.
Park, W. W., et al, Performance Advantages of Multithreaded Processors, Proceedings of the International Conference on Parallel Processing. 1991.
Smith, J. E., A Study of Branch Prediction Strategies, Proceedings of the 8th International Symposium on Computer Architecture - ISCA'81. Minneapolis. Minnesota. May, 1981.
Smith, J.E & Sohi, G.S., The Microarchitecture of SuperScalar Processors. Proceedings ofthe IEEE. 83(12), pp.1609-1624, December. 1995.
Tran. T. & Wu, C., Limitation of Superscalar Microprocessor Performance, Proceedings of the 25th Annual International Symposium on Microarchitecture. Portland, Oregon, Dec, 1992.
Tullsen, D. M., et all, Simultaneous Multithreading: Maximizing On-Chip Parallelism, Proceedings of the ISCA'95, Santa Margherita Ligure, Italy, Computer Architetcure News, n.2, v.23, 1995.
Wall. D. W."Limits of Instruction-Level Parallelism, Research Report, Digital, Western Research Laboratory. Palo Alto. California. June. 1993.
Wallace. S., Calder. B., Tullsen, D. M., Threaded Multiple Path Execution. Proceedings of the 25th International Symposium on Computer Architecture, June. 1998.
Butler. M., et all. Single Instruction Stream Parallelism ls Greater Than Two. Proceedings of the 18th Annual lnternational Symposium on Computer Architecture. Toronto, Canada, May. 1991.
Chakravarty, D. & Cannon. C., PowerPC: Concepts, Architecture, and Design, J. Ranade Workstations Series. McGraw-Hill. USA, Inc., p.363. 1994.
Govindarajan. R. & Nemawarkar. S. S., SMALL: A Scalable Multithreaded Architecture to Exploit Large Locality. Proceedings of the Fourth IEEE Symposium on Parallel and Distributed Processing. Dallas, TX, Dec, 1992.
Hirata, H. et all, An Elementary Processor Architecture with Simultaneous Instruction Issuing from Multiple Threads, Proceedings of the 19th Annual International Symposium on Computer Architecture. ACM & IEEE-CS. 1992.
Jouppi, N. P. & Wall. D. W., Available lnstruction-Level Parallelism for Superscalar and Superpipelined Machines, Research Report, Digital, Westem Research Laboratory, Palo Alto, California, July, 1989.
Laudon, J., et all, lnterleaving: A Multithreading Technique Targeting Multiprocessors and Workstations, Proceedings of the lnternational Conference on ASPLOS. Oct. 1994.
Lipasti. M.H. & Shen, J.P., Exceeding the Dataflow Limit via Value Prediction. 29th Micro, Paris, France, December, 1996.
MIPS R10000 Microprocessor User's Manual, Version 1.0, MIPS Technologies, Inc. North Shoreline, Mountain View, California, June, 1995.
Park, W. W., et al, Performance Advantages of Multithreaded Processors, Proceedings of the International Conference on Parallel Processing. 1991.
Smith, J. E., A Study of Branch Prediction Strategies, Proceedings of the 8th International Symposium on Computer Architecture - ISCA'81. Minneapolis. Minnesota. May, 1981.
Smith, J.E & Sohi, G.S., The Microarchitecture of SuperScalar Processors. Proceedings ofthe IEEE. 83(12), pp.1609-1624, December. 1995.
Tran. T. & Wu, C., Limitation of Superscalar Microprocessor Performance, Proceedings of the 25th Annual International Symposium on Microarchitecture. Portland, Oregon, Dec, 1992.
Tullsen, D. M., et all, Simultaneous Multithreading: Maximizing On-Chip Parallelism, Proceedings of the ISCA'95, Santa Margherita Ligure, Italy, Computer Architetcure News, n.2, v.23, 1995.
Wall. D. W."Limits of Instruction-Level Parallelism, Research Report, Digital, Western Research Laboratory. Palo Alto. California. June. 1993.
Wallace. S., Calder. B., Tullsen, D. M., Threaded Multiple Path Execution. Proceedings of the 25th International Symposium on Computer Architecture, June. 1998.
Publicado
28/09/1998
Como Citar
GONÇALVES, Ronaldo A. L.; NAVAUX, Philippe O. A..
SEMPRE: Uma Arquitetura SuperEscalar com Múltiplos Processos em Execução. In: INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE AND HIGH PERFORMANCE COMPUTING (SBAC-PAD), 10. , 1998, Búzios/RJ.
Anais [...].
Porto Alegre: Sociedade Brasileira de Computação,
1998
.
p. 257-266.
DOI: https://doi.org/10.5753/sbac-pad.1998.22675.
