SPECint95 Performance of an Implementation of the Dynamically Trace Scheduled VLIW Architecture

  • Alberto Ferreira de Souza University College London
  • Peter Rounce University College London

Resumo


Dynamically trace scheduled VLIW (DTSVLIW) architectures can be used to implement machines that execute code of current RISC or CISC instruction set architectures in a VLIW fashion, delivering instruction level parallelism with backward code compatibility. This paper presents preliminary SPECint95 performance mesuraments of the DTSVLIW architecture, obtained with a simulator which has been implemented in C.

Referências

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Publicado
28/09/1998
SOUZA, Alberto Ferreira de; ROUNCE, Peter. SPECint95 Performance of an Implementation of the Dynamically Trace Scheduled VLIW Architecture. In: INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE AND HIGH PERFORMANCE COMPUTING (SBAC-PAD), 10. , 1998, Búzios/RJ. Anais [...]. Porto Alegre: Sociedade Brasileira de Computação, 1998 . p. 185-188. DOI: https://doi.org/10.5753/sbac-pad.1998.22688.