Dimensionamento de processadores com arquitetura horizontal para exploração de micro e mesoparalelismo

  • Geraldo Lino de Campos USP

Abstract


Horizontal architectures can control several functional units independently, and usually have a single flow of control. As such, they exploit only the finer parallelism, and a large number of functional units is useless when the code contains control or data dependencies. Performance can be increased, with the same total hardware, if the functional units are divided in groups, each with a private register file and with an independent flow of control. This will neither impair the performance when many functional units are required, nor affect the cycle time adversely. Very important side effects are the reduction on the numberof ports in the central register file, with reduction of the instruction size as well. Results are presented for a processor showing that improvements in the range of 2.4 can be achieved in the geometric mean of performance when executing the Lawrence Livermore Kernels.

References

Campos, G. L., "Arquitetura Policíclica Assíncrona", Anais do III Simp. Brasileiro de Arquitetura de Computadores, 83-95, Rio de Janeiro, novembro de 1990

Campos, G.L., "Asynchronous Polycyclic Architecture: an overview", Proc. of the 12th Word Computer Congress, vol 1 - Algorithms, Software, Architecture, Madrid, Sept 1992.

Campos, G. L., "Asynchronous Polycyclic Architecture", Proc. of the 6th International Conference on Parallel Processing", Lyon, Sept 1992.

Dehnert, J. C., Hsu, P. Y.T., Bratt, J. P., "Overlapped Loop Support in the Cydra 5", 3rd Int. Conf. on Architectural Support for Programming Languages and Operating Systems, 26-38, April 1989

Fisher, J. A. "Very Long Instruction Word Architectures and the ELI-512", IEEE Cont. Proc. of the 10th Annual Int. Symp. on Comput. Architecture, 140-150, June 1983.

Jouppi, N. P. and Wall, D. W., "Available Instruction-level Parallelism for Superscalar and Superpipelined Machines", 3rd Int. Conference on Architectural Support for Programming Languages and Operating Systems, 272-282, April 1989.

McMahon, F. H. "The Livermore Fortran Kernels: A Computer Test of the Numerical Performance Range," Lawrence Livermore Nat'l Laboratory Report No. UCRL-53745, Livermore, CA, Dec. 1986.

Smith, M. D., Johnson, M. and Horowitz, M. A. "Limits on Multiple Instruction Issue", 3rd Int. Conference on Architectural Support for Programming Languages and Operating Systems, 290-302, April 1989.
Published
1992-10-26
CAMPOS, Geraldo Lino de. Dimensionamento de processadores com arquitetura horizontal para exploração de micro e mesoparalelismo. In: INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE AND HIGH PERFORMANCE COMPUTING (SBAC-PAD), 4. , 1992, São Paulo/SP. Anais [...]. Porto Alegre: Sociedade Brasileira de Computação, 1992 . p. 473-485. DOI: https://doi.org/10.5753/sbac-pad.1992.22729.