Primeiros Resultados da Proto-Arquitetura a Fluxo de Dados Wolf
Resumo
Este artigo apresenta a arquitetura preliminar definida para estudar características desejáveis para o processador Wolf. O projeto Wolf propõe-se a implementar e estudar as características de um supercomputador de alta velocidade baseado no modelo de fluxo de dados de granularidade variável. Os primeiros resultados das simulações dessa arquitetura são também apresentados e comparados com dados conhecidos. Para contextualizar a proposta Wolf no contexto da pesquisa contemporânea em fluxo de dados, o artigo inclui uma resenha dos principais projetos europeus americanos e japoneses.
Referências
M. Amamiya and R. Hasegawa, Dataflow Computing and Eager and Lazy Evaluation. J. New Generation Computers, 2(8):105-129, 1984.
Arvind, M. L. Dertouzos, R. S. Nikhil, and G. M. Papadopoulos. PROJECT DATAFLOW, a Parallel Computing System Based on the Monsoon Architecture and the Id Programming Language. Technical Report CSG Memo 285. LCS, MIT, 1988.
Arvind, V. Kathail, and K. Pingaley. A Dataflow Architecture With Tagged Tokens. CSG Memo 174, LCS, MIT, Cambridge, Mass., USA. Sep 1980.
M. Corsish, D. W. Wogan, and J. C. Jensen. The Texas Instruments Distributed Processor. In Proc. Lovisiana Computer Exposition, 189-193, Lafayette, LA, USA, Mar 1979.
D. E. Culler and G. M. Papadopoulos. The Explicit Token Store. J. Paralle and Distributed Computing, 10(4), Jan 1991.
J. B. Dennis. Data Flow Computation. In M. Broy, editor, NATO ASI Series, v.F14, Control Flow and Data Flow: Concepts of Distributed Programming, 346-397. Springer- Verlag, Berlin, 1985.
J. F. Foley. Manchester Dataflow Machine: Benchmark Test Evaluation Report. Internal Report UMCS-89-11-1, DCS, Univ. Manchester, England, Nov 1989.
V. G. Grafe and J. E. Hoch. Implementation of the Epsilon Dataflow Processor. In Proc. 23rd Hawaii Int. Conf. on System Sciences, 1990.
V. G. Grafe and J. E. Hoch. The Epsilon-2 Multiprocessor System. J. Parallel and Distributed Computing, 10(4):309-318, Dec 1990.
J. R. Gurd, I. Watson, and J, R. W. Glauert. A Multilayered Dataflow Computer Architecture. Internal report, DCS, Univ. Manchester, Mar 1980.
K. Hiraki, T. Shimada, and K. Nishida. A Hardware Design of the SIGMA-1 - A Data Flow Computer for Scientific Computations. In Proc. Int. Conf. on Parallel Processing, 524-531. IEEE, 1984.
R. A. Iannucci. A Dataflow/von Neumann Hybrid Architecture. Technical Report TR-418, LCS, MIT, Cambridge, Mass. USA, 1988.
C. F. Joerg. Design and Implementation of a Packet Switched Routing Chip. Masters' thesis, Dept. Electrical Eng. and Computer Science. MIT, Cambridge. Mass.. USA, 1988,
M. Kishi, H. Yasuhara. and Y. Kawamura. DDDP: A Distributed Data Driven Processor. In Proc. 10th Annual Int. Symp. Computer Architecture, 236-242. IEEE, 1983.
G. M. Papadopoulos. Implementation of a General Purpose Dataflow Multiprocessor, PhD Thesis. Technical Report TR 432, LCS, MIT, Cambridge. Mass., USA. Sep 1988.
C. A. Ruggiero. Throttle Mechanisms for the Manchester Dataflow Machine. Technical Report Series UMCS-87-8-1, DCS, Univ. Manchester, England. Jul 1987.
A. Garcia Neto Distributed Simulation Using "Relaxed Timing" PhD Thesis. DCS, Univ. Manchester, England, 1991.
T. Suzuki, K. Kurihara, H. Tanaka. and T. Moto-oka. Procedure Level Data Flow Processing on Dynamic Structure Multimicroprocessors. J. Information Processing, 1(5):11-16, 1982.
T. Shimada T. Yuba et al. Dataflow Computer Development in Japan. ACM, 140-147, 1990.
N. Takahashi and M. Amamiya. A Data Flow Processor Array System - Design and Analysis. In Proc. IEEE 10th Annual Int. Symp. Computer Architecture, 243-250. IEEE. 1983.
T. Temma, S. Hasegawa. and S. Hanaki. Dataflow Processor for Image Processing. Proc. on Mini and Microcomputers, 5(3):52-56, 1980.
H Terada, H Nisikawa nd K. Asada, S. Matsumoto, S. Miyata, S. Komori, and K. Shima, VLSI Design of a One-Chip Data-Driven Processor: Q-v1. In Proc. Fall Joint Computer Conf.. ACM/IEEE, 1987.
F. J. Valente. Estudo de arquiteturas risc, Master's thesis, DFCM, IFQSC, Universidade de S ao Paulo, 1991.
A. H. Veen and R. van den Bom. The RC Compiler for the DTN Dataflow Computer. J. Parallel and Distributed Computing, 10(4):319-332. Dec 1990.
Y. Yamagushi, K. Toda, J. Herath, and T. Yuba. EM-3: A LISP-Based Data-Driven Machine, In Proc. Int. Conf. on Fifth Generation Computer Systems, 524-532. ICOT, 1984.
Arvind, M. L. Dertouzos, R. S. Nikhil, and G. M. Papadopoulos. PROJECT DATAFLOW, a Parallel Computing System Based on the Monsoon Architecture and the Id Programming Language. Technical Report CSG Memo 285. LCS, MIT, 1988.
Arvind, V. Kathail, and K. Pingaley. A Dataflow Architecture With Tagged Tokens. CSG Memo 174, LCS, MIT, Cambridge, Mass., USA. Sep 1980.
M. Corsish, D. W. Wogan, and J. C. Jensen. The Texas Instruments Distributed Processor. In Proc. Lovisiana Computer Exposition, 189-193, Lafayette, LA, USA, Mar 1979.
D. E. Culler and G. M. Papadopoulos. The Explicit Token Store. J. Paralle and Distributed Computing, 10(4), Jan 1991.
J. B. Dennis. Data Flow Computation. In M. Broy, editor, NATO ASI Series, v.F14, Control Flow and Data Flow: Concepts of Distributed Programming, 346-397. Springer- Verlag, Berlin, 1985.
J. F. Foley. Manchester Dataflow Machine: Benchmark Test Evaluation Report. Internal Report UMCS-89-11-1, DCS, Univ. Manchester, England, Nov 1989.
V. G. Grafe and J. E. Hoch. Implementation of the Epsilon Dataflow Processor. In Proc. 23rd Hawaii Int. Conf. on System Sciences, 1990.
V. G. Grafe and J. E. Hoch. The Epsilon-2 Multiprocessor System. J. Parallel and Distributed Computing, 10(4):309-318, Dec 1990.
J. R. Gurd, I. Watson, and J, R. W. Glauert. A Multilayered Dataflow Computer Architecture. Internal report, DCS, Univ. Manchester, Mar 1980.
K. Hiraki, T. Shimada, and K. Nishida. A Hardware Design of the SIGMA-1 - A Data Flow Computer for Scientific Computations. In Proc. Int. Conf. on Parallel Processing, 524-531. IEEE, 1984.
R. A. Iannucci. A Dataflow/von Neumann Hybrid Architecture. Technical Report TR-418, LCS, MIT, Cambridge, Mass. USA, 1988.
C. F. Joerg. Design and Implementation of a Packet Switched Routing Chip. Masters' thesis, Dept. Electrical Eng. and Computer Science. MIT, Cambridge. Mass.. USA, 1988,
M. Kishi, H. Yasuhara. and Y. Kawamura. DDDP: A Distributed Data Driven Processor. In Proc. 10th Annual Int. Symp. Computer Architecture, 236-242. IEEE, 1983.
G. M. Papadopoulos. Implementation of a General Purpose Dataflow Multiprocessor, PhD Thesis. Technical Report TR 432, LCS, MIT, Cambridge. Mass., USA. Sep 1988.
C. A. Ruggiero. Throttle Mechanisms for the Manchester Dataflow Machine. Technical Report Series UMCS-87-8-1, DCS, Univ. Manchester, England. Jul 1987.
A. Garcia Neto Distributed Simulation Using "Relaxed Timing" PhD Thesis. DCS, Univ. Manchester, England, 1991.
T. Suzuki, K. Kurihara, H. Tanaka. and T. Moto-oka. Procedure Level Data Flow Processing on Dynamic Structure Multimicroprocessors. J. Information Processing, 1(5):11-16, 1982.
T. Shimada T. Yuba et al. Dataflow Computer Development in Japan. ACM, 140-147, 1990.
N. Takahashi and M. Amamiya. A Data Flow Processor Array System - Design and Analysis. In Proc. IEEE 10th Annual Int. Symp. Computer Architecture, 243-250. IEEE. 1983.
T. Temma, S. Hasegawa. and S. Hanaki. Dataflow Processor for Image Processing. Proc. on Mini and Microcomputers, 5(3):52-56, 1980.
H Terada, H Nisikawa nd K. Asada, S. Matsumoto, S. Miyata, S. Komori, and K. Shima, VLSI Design of a One-Chip Data-Driven Processor: Q-v1. In Proc. Fall Joint Computer Conf.. ACM/IEEE, 1987.
F. J. Valente. Estudo de arquiteturas risc, Master's thesis, DFCM, IFQSC, Universidade de S ao Paulo, 1991.
A. H. Veen and R. van den Bom. The RC Compiler for the DTN Dataflow Computer. J. Parallel and Distributed Computing, 10(4):319-332. Dec 1990.
Y. Yamagushi, K. Toda, J. Herath, and T. Yuba. EM-3: A LISP-Based Data-Driven Machine, In Proc. Int. Conf. on Fifth Generation Computer Systems, 524-532. ICOT, 1984.
Publicado
1992-10-26
Como Citar
GARCIA NETO, A.; CAVENAGHI, M. A..
Primeiros Resultados da Proto-Arquitetura a Fluxo de Dados Wolf.
Anais do International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD), [S.l.], p. 503-514, out. 1992.
ISSN 0000-0000.
Disponível em: <https://sol.sbc.org.br/index.php/sbac-pad/article/view/22731>. Acesso em: 14 maio 2024.
doi: https://doi.org/10.5753/sbac-pad.1992.22731.
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