Aplicação da Tecnologia de Compiladores Paralelizantes para Gerência de Memória: um Estudo de Caso

  • Edson Toshimi Midorikawa USP

Abstract


Modern processor design strategies have focused on increasing the computacional power. The result is an imbalance between computational speed and memory speed. This paper presents a case study on application of parallelizing compiler technology to memory-hierarchy management. The results reveal that the use of compiler optimizations to memory-bound programs promises very good results.

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Published
1993-09-07
MIDORIKAWA, Edson Toshimi. Aplicação da Tecnologia de Compiladores Paralelizantes para Gerência de Memória: um Estudo de Caso. In: INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE AND HIGH PERFORMANCE COMPUTING (SBAC-PAD), 5. , 1993, Florianópolis/SC. Anais [...]. Porto Alegre: Sociedade Brasileira de Computação, 1993 . p. 259-274. DOI: https://doi.org/10.5753/sbac-pad.1993.23037.