Prova de Correção de Mecanismos de Controle de Coerência em Multiprocessadores
Resumo
Em ambientes multicache, cada processador tem a ele associado uma memória cache privada, utilizada no armazenamento de dados provenientes da memória global. A consistência entre as cópias de um dado, que em um determinado momento pode existir em mais de uma memória cache, e o dado armazenado na memória global é garantida por um mecanismo de controle de coerência, que pode variar de multiprocessador para multiprocessador. Neste artigo nós propomos uma metodologia de prova de correção de mecanismos de controle de coerência para ambientes multicache orientados a barramento.
Referências
Archibald, J.,Baer, J..'Cache Coherence Protocols: Evaluation Using a Multiprocessor Simulation Model',ACM Trans. on Computers,Vol. 4,No. 4,Nov. 86,pp 273-298
Brantley, W. Cc. et all,'RP3 Processor-Memory Element', IEEE Int. Conf. on Parallel Processing, August 20-23,1985,pp 185-221
Dubois, M., Briggs, F,'Effects of Cache Coherency in Multiprocessors', IEEE Trans. on Computers,Vol. C-31,No. 11,Nov. 82,pp 1083-1098
Dubois, M., 'Effect of Invalidations on Hit Ratio of Cache-Based Multiprocessors',Proc. of the 1987 Int. Conf. on Parallel Processing, August 17-21,1987,pp 225-257
Dubois, M.,'Throughput Analysis of Cache-Based Multiprocessors with Multiple Buses', IEEE Trans. on Computers,Vol. 37,No. 1,Jan. 88,pp 58-70
Dubois, M., Wang, J.,'Analytical Modelling of Data Sharing in Cache-Based Multiprocessors',Technical Report No. CENG 89-18,University of Southern California,June 89
Goodman, J. R.,'Using Cache Memory to Reduce Processor-Memory Traffic',Proc. of the 10th Int. Symp. on Computer Architecture, IEEE,New York,1983,pp 124-131
Smith, A. J.,'Cache Memories',Computing Surveys,Vol. 14,No. 3,Sept. 82,pp 473-530
Vernon, M., Holliday, M.,'Performance Analysis of Multiprocessors Cache Consistency Protocols using Generalized Time Petri Nets',Proc. of Performance 86 and ACM Sigmetrics 1986 Joint Conf. on Computer Performance Modelling, Measurement and Evaluation, Raleigh, N. C.,May 86, pp 9-17
Vernon, M., Lazowska, E., Zahorjan, J.,'An Accurate and Efficient Performance Analysis Technique for Multiprocessor Snooping Cache-Consistency Protocols' ,Technical Report 88-03-04, University of Washington,March 88
Brantley, W. Cc. et all,'RP3 Processor-Memory Element', IEEE Int. Conf. on Parallel Processing, August 20-23,1985,pp 185-221
Dubois, M., Briggs, F,'Effects of Cache Coherency in Multiprocessors', IEEE Trans. on Computers,Vol. C-31,No. 11,Nov. 82,pp 1083-1098
Dubois, M., 'Effect of Invalidations on Hit Ratio of Cache-Based Multiprocessors',Proc. of the 1987 Int. Conf. on Parallel Processing, August 17-21,1987,pp 225-257
Dubois, M.,'Throughput Analysis of Cache-Based Multiprocessors with Multiple Buses', IEEE Trans. on Computers,Vol. 37,No. 1,Jan. 88,pp 58-70
Dubois, M., Wang, J.,'Analytical Modelling of Data Sharing in Cache-Based Multiprocessors',Technical Report No. CENG 89-18,University of Southern California,June 89
Goodman, J. R.,'Using Cache Memory to Reduce Processor-Memory Traffic',Proc. of the 10th Int. Symp. on Computer Architecture, IEEE,New York,1983,pp 124-131
Smith, A. J.,'Cache Memories',Computing Surveys,Vol. 14,No. 3,Sept. 82,pp 473-530
Vernon, M., Holliday, M.,'Performance Analysis of Multiprocessors Cache Consistency Protocols using Generalized Time Petri Nets',Proc. of Performance 86 and ACM Sigmetrics 1986 Joint Conf. on Computer Performance Modelling, Measurement and Evaluation, Raleigh, N. C.,May 86, pp 9-17
Vernon, M., Lazowska, E., Zahorjan, J.,'An Accurate and Efficient Performance Analysis Technique for Multiprocessor Snooping Cache-Consistency Protocols' ,Technical Report 88-03-04, University of Washington,March 88
Publicado
07/11/1990
Como Citar
NUNES, Adélia Cecília G.; MENASCÉ, Daniel A..
Prova de Correção de Mecanismos de Controle de Coerência em Multiprocessadores. In: INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE AND HIGH PERFORMANCE COMPUTING (SBAC-PAD), 3. , 1990, Rio de Janeiro/RJ.
Anais [...].
Porto Alegre: Sociedade Brasileira de Computação,
1990
.
p. 151-162.
DOI: https://doi.org/10.5753/sbac-pad.1990.23115.
