Um Esquema de Reconfiguração Heurístico para um Computador Paralelo Tolerante a Falhas
Resumo
Este artigo descreve uma arquitetura altamente reconfigurével para um arranjo retangular bi-dimensional de processadores poderosos. Devido ao alto grau de reconfigurabilidade, a arquitetura pode prover tolerancia a falhas com eficiente utilização dos processadores e servir de suporte a programas de aplicação que requerem diferentes estruturas de interconexão. O esquema de reconfiguração considera o arranjo físico como um grafo qualquer, podendo ser aplicado não apenas a arranjos retangulares. Em termos de considerações de falhas, supomos não apenas falhas de processadores, mas também as de chaves e canais físicos de comunicação. Nesses dois aspectos o presente trabalho distingue-se dos anteriores.
Referências
Kwang, J.H. e Raghavendra, C.S. VLSI Implementation of Fault-Tolerant Systolic Arrays. Proc. International Conference on Computer Design, October, 1986, pp. 110-113.
Negrini, Ras Sami, M. e Stefanelli, R. "Fault Tolerance Techniques for Array Structures used in Supercomputing". Computer Magazine 19, 2 (February 1986), pp. 78-87.
Snyder, L. "Introduction to the Configurable, Highly Parallel Computer". Computer 15, 1 (January 1982), pp. 47-56.
Annaratone, M., Arnould, E., Gross, T., Kung, H.T., Lam, M. Menzilcioglu, O. e Webb, J. "The Warp Computer: Architecture, Implementation and Performance". IEEE Transactions on Computers C-36, 12 (December 1987), Pp. 1523-1538.
Negrini, Rey Sami, M.G., Stefanelli, R. Fault Tolerance Approaches for VLSI/WSI Arrays. Proc. IEEE Phoenix Conf. on Comp. and Communication, 1985, pp. 460-468.
Singh, A.D. An Area Efficient Redundancy Scheme for Wafer Scale Processor Arrays. Proc. of International Conference on Computer Design, October, 1985, pp. 505-509.
Bruegge, B., Chang, C., Cohn, R., Gross, T., Lam, M., Lieu, P. Noaman, A. e Yam, D. Programming Warp. COMPCON Spring '87, IEEE Computer Society, 1987.
Kung, H.T. e Menzilcioglu, O. A General Switch Architecture for Fault-Tolerant VLSI Processor Arrays. Proceedings of International Symposium on VLSI Technology, Systems and Applications, May, 1987, pp. 211-217.
Shombert, L.A. Using Redundancy for Testable and Repairable Systolic Arrays. Ph.D. thesis, Carnegie Mellon University, August, 1985.
Kung, H.T. e Menzilcioglu, O. Virtual Channels for Fault-Tolerant Programmable Two-Dimensional Processor Arrays. Tech. Report CMU-CS-87-171, Carnegie Mellon University, December, 1986.
Wu, C.L. e Feng, TS Interconnection Networks for Parallel and Distributed Processing. IEEE. Computer Society Press, 1984.
Lombardi, F., Negrini, R., Sami, M.G., Stefanelli, Ha Reconfiguration of VLSI Arrays: a Covering Approach. Proceedings of 17th International Symposium on Fault-Tolerant Computing, 1987, pp. 251-256.
Kung, H.T. The Structure of Parallel Algorithms. Advances in Computers, Volume 19, New York, 1980, pp. 65-112.
Garey, M.R. and Johnson, D.S. Computers and Intractability - A guide to the Theory of NP-Completeness, W.H. Freeman and Company, San Francisco, 1979.
Cohn, R., Kung, H.T., Menzilcioglu, O. e Song, S.W. A Highly Reconfigurable Array of Powerful Processors. Proceedings of SPIE Symposium, Vol. 975, Advanced Algorithms and Architectures for Signal Processing III, Society of Photo-Optical Instrumentation Engineers, August, 1988.
Negrini, Ras Sami, M. e Stefanelli, R. "Fault Tolerance Techniques for Array Structures used in Supercomputing". Computer Magazine 19, 2 (February 1986), pp. 78-87.
Snyder, L. "Introduction to the Configurable, Highly Parallel Computer". Computer 15, 1 (January 1982), pp. 47-56.
Annaratone, M., Arnould, E., Gross, T., Kung, H.T., Lam, M. Menzilcioglu, O. e Webb, J. "The Warp Computer: Architecture, Implementation and Performance". IEEE Transactions on Computers C-36, 12 (December 1987), Pp. 1523-1538.
Negrini, Rey Sami, M.G., Stefanelli, R. Fault Tolerance Approaches for VLSI/WSI Arrays. Proc. IEEE Phoenix Conf. on Comp. and Communication, 1985, pp. 460-468.
Singh, A.D. An Area Efficient Redundancy Scheme for Wafer Scale Processor Arrays. Proc. of International Conference on Computer Design, October, 1985, pp. 505-509.
Bruegge, B., Chang, C., Cohn, R., Gross, T., Lam, M., Lieu, P. Noaman, A. e Yam, D. Programming Warp. COMPCON Spring '87, IEEE Computer Society, 1987.
Kung, H.T. e Menzilcioglu, O. A General Switch Architecture for Fault-Tolerant VLSI Processor Arrays. Proceedings of International Symposium on VLSI Technology, Systems and Applications, May, 1987, pp. 211-217.
Shombert, L.A. Using Redundancy for Testable and Repairable Systolic Arrays. Ph.D. thesis, Carnegie Mellon University, August, 1985.
Kung, H.T. e Menzilcioglu, O. Virtual Channels for Fault-Tolerant Programmable Two-Dimensional Processor Arrays. Tech. Report CMU-CS-87-171, Carnegie Mellon University, December, 1986.
Wu, C.L. e Feng, TS Interconnection Networks for Parallel and Distributed Processing. IEEE. Computer Society Press, 1984.
Lombardi, F., Negrini, R., Sami, M.G., Stefanelli, Ha Reconfiguration of VLSI Arrays: a Covering Approach. Proceedings of 17th International Symposium on Fault-Tolerant Computing, 1987, pp. 251-256.
Kung, H.T. The Structure of Parallel Algorithms. Advances in Computers, Volume 19, New York, 1980, pp. 65-112.
Garey, M.R. and Johnson, D.S. Computers and Intractability - A guide to the Theory of NP-Completeness, W.H. Freeman and Company, San Francisco, 1979.
Cohn, R., Kung, H.T., Menzilcioglu, O. e Song, S.W. A Highly Reconfigurable Array of Powerful Processors. Proceedings of SPIE Symposium, Vol. 975, Advanced Algorithms and Architectures for Signal Processing III, Society of Photo-Optical Instrumentation Engineers, August, 1988.
Publicado
26/09/1988
Como Citar
SONG, S. W..
Um Esquema de Reconfiguração Heurístico para um Computador Paralelo Tolerante a Falhas. In: INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE AND HIGH PERFORMANCE COMPUTING (SBAC-PAD), 2. , 1988, São José dos Campos/SP.
Anais [...].
Porto Alegre: Sociedade Brasileira de Computação,
1988
.
p. 170-179.
DOI: https://doi.org/10.5753/sbac-pad.1988.23534.
