An advanced filtering TLB for low power consumption

• Jin-Hyuck Choi Yonsei University
• Jung-Hoon Lee Yonsei University
• Gi-Ho Park SOC center
• Shin-Dug Kim Yonsei University

Resumo

This research is to design a new two-level TLB (translation look-aside buffer) architecture that integrates a 2-way banked filter TLB with a 2-way banked main TLB. One of the main objectives is to reduce power consumption in embedded processors by distributing the accesses to the TLB entries across several banks in a balanced manner. Thus, an advanced filtering technique is devised to reduce power dissipation by adopting a sub-bank structure at the filter TLB. And also a bank-associative structure is applied to each level of the TLB hierarchy. Simulation result shows that the miss ratio and Energy*Delay product can be improved by 59.26% and 24.9%, respectively, compared with a micro TLB with 4-32 entries, and 40.81% and 12.18%, compared with a micro TLB with 16-32 entries.

Palavras-chave: Filtering, Energy consumption, Random access memory, Filter bank, Clocks, Capacitance, Cities and towns, Power dissipation, Circuits, Reduced instruction set computing