High Level Power and Energy Exploration Using ArchC

  • T. Gupta LIST, CEA, Gif-sur-Yvette
  • C. Bertolini LIST, CEA, Gif-sur-Yvette
  • O. Heron LIST, CEA, Gif-sur-Yvette
  • N. Ventroux LIST, CEA, Gif-sur-Yvette
  • T. Zimmer Université Bordeaux 1
  • F. Marc Université Bordeaux 2

Abstract


With the increase in the design complexity of MPSoC architectures, estimating power consumption is very complex and time consuming at lower level of abstraction. We propose a methodology using ArchC named Power-ArchC for a fast high-level estimation of processor power consumption. Power values are obtained by an instruction level power characterization at gate level. The requirements for power evaluation infrastructure are compatible processor models written in ArchC and RTL, and the Technology library. We show power results for a 32-bit MIPS processor with different benchmarks, based on 45nm technology.
Keywords: Integrated circuit modeling, Logic gates, Computer architecture, Power demand, Computational modeling, Accuracy, Estimation, ArchC, PowerArchC, power consumption, energy, MIPS R3000, ILPC
Published
2010-10-27
How to Cite

Select a Format
GUPTA, T.; BERTOLINI, C.; HERON, O.; VENTROUX, N.; ZIMMER, T.; MARC, F.. High Level Power and Energy Exploration Using ArchC. In: INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE AND HIGH PERFORMANCE COMPUTING (SBAC-PAD), 22. , 2010, Petrópolis/RJ. Anais [...]. Porto Alegre: Sociedade Brasileira de Computação, 2010 . p. 25-32.