Value Reuse Potential in ARM Architectures

• Rodrigo C. De Moura UFPEL
• Giovane O. Torres UFPEL
• Maurício L. Pilla UFPEL
• Laércio L. Pilla UFSC
• Amarildo T. Da Costa IME
• Felipe M. G. França UFRJ

Resumo

Code execution in modern superscalar processors is inherently redundant. Many instructions execute repeatedly with the same inputs, producing the same outputs, thus wasting resources in the process. Value reuse techniques memorize previous executions of instructions, blocks or traces which may be reused if they appear again with the same input contexts. Although trace reuse techniques show great potential for both performance and energy consumption improvement, they have not been studied yet in one of the most widely available computer architectures - the ARM architecture. In this paper, the main issues with reusing traces in instruction sets with conditional execution are revisited. Afterwards, the reuse potential in the benchmark suite MiBench is analyzed varying (i) how traces are generated, and (ii) the size of reuse tables. Our results show that a memoization table of 32 KiB allows to reuse 18.36% of the total instructions on average.

Palavras-chave: Computer architecture, Registers, Context, Pipelines, Instruction sets, Computers, value reuse, ARM architecture