Memory Latency: to Tolerate or to Reduce?

• Amol Bakshi University of Soutern California
• Jean-Luc Gaudiot University of Soutern California
• Wen-Yen Lin University of Soutern California
• Manil Makhija University of Soutern California
• Viktor K. Prasana University of Soutern California
• Wonwoo Ro University of Soutern California
• Chulho Shin University of Soutern California

DOI: https://doi.org/10.5753/sbac-pad.2000.41199

Resumo

It has become a truism that the gap between processor speed and memory access latency is continuing to increase at a rapid rate. This paper presents some of the architecture strategies which are used to bridge this gap. They are mostly of two kinds: memory latency reducing approaches such as employed in caches and HiDISC: (Hierarchical Decoupled Architecture) or memory latency tolerating schemes such as SMT (Simultaneous Multithreading) or ISSC (I-structure software cache). Yet a third technique reduces the latency by integrating on the same chip processor and DRAM. Finally, algorithmic techniques to improve cache utilization and reduce average memory access latency for traditional cache architectures are discussed.

Palavras-chave: Memory Access Latency, Simultaneous Multithreading, Decoupled Architecture, Memory Bandwidth, Processing in Memory

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