Analyzing Branch Prediction Impact on the Effectiveness of Instruction Prefetch
Resumo
In order to provide a high instruction throughput for advanced superscalar models, L1 caches must achieve a low miss rate with no increase orminimum change in L1 capability. Prefetch mechanism anticipate data from memory to L1 caches ahead of its request by the CPU instruction executing flow. These kind of schemes reduce the miss occurence as well as help to hide the memory access latency. The wrong path prefetch anticipates the next block and also the taken target of a branch. This work analyzes how the branch prediction may influence in the performance of this prefetch scheme. The number of wasted cycles and the effects of cache pollution and prefetch overlap are also presented.
Palavras-chave:
Prefetch mechanisms, branch prediction, superscalar architectures, cache memory
Referências
BURGER, Doug; AUSTIN, Todd. The SimpleScalar Tool Set, version 2.0. Madison: Computer Sciences Department/ University of Wisconsin-Madison. (Technical Report).
FERNÁNDEZ, Agustin. Un análisis quantitativo del Spec95. Barcelona: Universitat Politècnica de Catalunya. (Technical Report).
HOREL, Tim; LAUTHERBACH, Gary. UltraSparc-III: designing third-generation 64-bit performance. IEEE Micro, v.19, n.13, p.73–85, May/June 1999.
HSU, Peter. Design of the TFP microprocessor. IEEE Micro, Los Alamitos, v.14, n.2, p.23–33, March/April 1994.
INTEL CORPORATION. Pentium III processor for the SC242 at 450 MHz to 866 MHz. [link] (March 2000).
JOHNSON, Mike. Superscalar microprocessor design. Englewood Cliffs: Prentice Hall, 1991.
KESSLER, Richard E. The Alpha 21264 microprocessor. IEEE Micro, Los Alamitos, v.19, n.2, March/April 1999.
PIERCE, James E. Cache behaviour in the presence of speculative execution – The Benefits of Misprediction. Ann Arbor: Department of Computer Science and Engineering/University of Michigan, 1995. (Ph.D. Thesis).
SANTOS, Tatiana G. S. dos. Analyzing the prefetch mechanisms on the RISC superscalar microprocessors memory hierarchy. Porto Alegre: Institute of Computer Science/Federal University of Rio Grande do Sul, 2000. (M.Sc. Thesis). (In Portuguese).
STONE, Harold. High performance computing. Englewood Cliffs: Prentice Hall, 1993.
FERNÁNDEZ, Agustin. Un análisis quantitativo del Spec95. Barcelona: Universitat Politècnica de Catalunya. (Technical Report).
HOREL, Tim; LAUTHERBACH, Gary. UltraSparc-III: designing third-generation 64-bit performance. IEEE Micro, v.19, n.13, p.73–85, May/June 1999.
HSU, Peter. Design of the TFP microprocessor. IEEE Micro, Los Alamitos, v.14, n.2, p.23–33, March/April 1994.
INTEL CORPORATION. Pentium III processor for the SC242 at 450 MHz to 866 MHz. [link] (March 2000).
JOHNSON, Mike. Superscalar microprocessor design. Englewood Cliffs: Prentice Hall, 1991.
KESSLER, Richard E. The Alpha 21264 microprocessor. IEEE Micro, Los Alamitos, v.19, n.2, March/April 1999.
PIERCE, James E. Cache behaviour in the presence of speculative execution – The Benefits of Misprediction. Ann Arbor: Department of Computer Science and Engineering/University of Michigan, 1995. (Ph.D. Thesis).
SANTOS, Tatiana G. S. dos. Analyzing the prefetch mechanisms on the RISC superscalar microprocessors memory hierarchy. Porto Alegre: Institute of Computer Science/Federal University of Rio Grande do Sul, 2000. (M.Sc. Thesis). (In Portuguese).
STONE, Harold. High performance computing. Englewood Cliffs: Prentice Hall, 1993.
Publicado
24/10/2000
Como Citar
SANTOS, Tatiana G. S. dos; PILLA, Maurício L.; DAL PIZZOL, Guilherme; BAMPI, Sergio; NAVAUX, Philippe O. A..
Analyzing Branch Prediction Impact on the Effectiveness of Instruction Prefetch. In: INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE AND HIGH PERFORMANCE COMPUTING (SBAC-PAD), 12. , 2000, São Pedro/SP.
Anais [...].
Porto Alegre: Sociedade Brasileira de Computação,
2000
.
p. 147-154.
DOI: https://doi.org/10.5753/sbac-pad.2000.41215.
