API para Monitoramento de Desempenho em Sistemas Multicore Embarcados
Resumo
Contadores de desempenho de hardware (CDHs) são registradores disponíveis nos processadores atuais capazes de contar eventos microarquiteturais. Em especial para aplicações embarcadas de tempo-real implementadas em processadores multicore, os CDHs podem ajudar o SO a obter uma visão precisa dos recursos físicos que estão sendo compartilhados pelas threads do sistema e que podem causar a perda de deadlines. Este artigo apresenta uma interface de CDHs especificamente projetada para sistemas embarcados. O uso da interface é demonstrado através de um benchmark que compartilha dados entre duas threads executando em diferentes cores. Como resultado, o SO é capaz de obter uma visão correta sobre o comportamento da aplicação.
Referências
S. Mohan M. Caccamo L. Sha R. Pellizzoni G. Arundale R. Kegley and D. de Niz "Using multicore architectures in cyber-physical systems " in Workshop on Developing Dependable and Secure Automotive Cyber-Physical Systems from Components Michigan USA Mar 2011.
C. Cullmann C. Ferdinand G. Gebhard D. Grund C. Maiza J. Reineke B. Triquet S. Wegener and R. Wilhelm "Predictability considerations in the design of multi-core embedded systems " Ingénieurs de l'Automobile vol. 807 pp. 36- 42 September 2010.
S. Zhuravlev S. Blagodurov and A. Fedorova "Addressing shared resource contention in multicore processors via scheduling " in Proceedings of the 15th edition of ASPLOS on Architectural support for programming languages and operating systems ser. ASPLOS '10 2010 pp. 129-142.
S. Boyd-Wickizer A. T. Clements Y. Mao A. Pesterev M. F. Kaashoek R. Morris and N. Zeldovich "An Analysis of Linux Scalability to Many Cores " in OSDI 2010: Proceedings of the 9th USENIX conference on Operating Systems Design and Implementation 2010.
F. V. Polpeta and A. A. Fröhlich "Hardware mediators: a portability artifact for component-based systems " in In Proceedings of the International Conference on Embedded and Ubiquitous Computing ser. Lecture Notes in Computer Science vol. 3207. Aizu Japan: Springer Berlin / Heidelberg 2004 pp. 45-53.
A. A. Fröhlich Application-Oriented Operating Systems ser. GMD Research Series. Sankt Augustin: GMD - Forschungszentrum Informationstechnik Aug. 2001 no. 17.
H. Marcondes A. S. Hoeller L. F. Wanner and A. A. Fröhlich "Operating systems portability: 8 bits and beyond " in ETFA '06: IEEE Conference on Emerging Technologies and Factory Automation Sept. 2006 pp. 124 -130.
Intel Corporation Intel® 64 and IA-32 Architectures Software Developer's Manual January 2011 no. 253668-037US.
R. K. Malladi Using Intel® VTuneTM Performance Analyzer Events/Ratios Optimizing Applications no. Intel® White Paper.
J. Dongarra K. London S. Moore P. Mucci D. Terpstra H. You and M. Zhou "Experiences and lessons learned with a portable interface to hardware performance counters " in Proceedings of the 17th International Symposium on Parallel and Distributed Processing ser. IPDPS '03. Washington DC USA: IEEE Computer Society 2003 pp. 289.2-.
P. J. Drongowski An introduction to analysis and optimization with AMD CodeAnalyst Performance Analyzer September 2008.
F. Bellosa and M. Steckermeier "The performance implications of locality information usage in shared-memory multiprocessors " Journal of Parallel Distributed Computing vol. 37 pp. 113-121 August 1996. (Pubitemid 126167771)
B. Weissman "Performance counters and state sharing annotations: a unified approach to thread locality " SIG. Operat. Sys. Rev. vol. 32 pp. 127-138 October 1998.
D. Tam R. Azimi and M. Stumm "Thread clustering: sharing-aware scheduling on smp-cmp-smt multiprocessors " SIG. Operat. Sys. Rev. vol. 41 pp. 47-58 March 2007. (Pubitemid 47281574)
R. West P. Zaroo C. A. Waldspurger and X. Zhang "Online cache modeling for commodity multicore processors " SIGOPS Ope. Sys. Rev. vol. 44 pp. 19-29 December 2010.
J. M. Calandrino and J. H. Anderson "On the design and implementation of a cache-aware multicore real-time scheduler " in Proc. of the 21st Euromicro Conference on Real-Time Systems Washington DC USA 2009 pp. 194-204.
C. Cullmann C. Ferdinand G. Gebhard D. Grund C. Maiza J. Reineke B. Triquet S. Wegener and R. Wilhelm "Predictability considerations in the design of multi-core embedded systems " Ingénieurs de l'Automobile vol. 807 pp. 36- 42 September 2010.
S. Zhuravlev S. Blagodurov and A. Fedorova "Addressing shared resource contention in multicore processors via scheduling " in Proceedings of the 15th edition of ASPLOS on Architectural support for programming languages and operating systems ser. ASPLOS '10 2010 pp. 129-142.
S. Boyd-Wickizer A. T. Clements Y. Mao A. Pesterev M. F. Kaashoek R. Morris and N. Zeldovich "An Analysis of Linux Scalability to Many Cores " in OSDI 2010: Proceedings of the 9th USENIX conference on Operating Systems Design and Implementation 2010.
F. V. Polpeta and A. A. Fröhlich "Hardware mediators: a portability artifact for component-based systems " in In Proceedings of the International Conference on Embedded and Ubiquitous Computing ser. Lecture Notes in Computer Science vol. 3207. Aizu Japan: Springer Berlin / Heidelberg 2004 pp. 45-53.
A. A. Fröhlich Application-Oriented Operating Systems ser. GMD Research Series. Sankt Augustin: GMD - Forschungszentrum Informationstechnik Aug. 2001 no. 17.
H. Marcondes A. S. Hoeller L. F. Wanner and A. A. Fröhlich "Operating systems portability: 8 bits and beyond " in ETFA '06: IEEE Conference on Emerging Technologies and Factory Automation Sept. 2006 pp. 124 -130.
Intel Corporation Intel® 64 and IA-32 Architectures Software Developer's Manual January 2011 no. 253668-037US.
R. K. Malladi Using Intel® VTuneTM Performance Analyzer Events/Ratios Optimizing Applications no. Intel® White Paper.
J. Dongarra K. London S. Moore P. Mucci D. Terpstra H. You and M. Zhou "Experiences and lessons learned with a portable interface to hardware performance counters " in Proceedings of the 17th International Symposium on Parallel and Distributed Processing ser. IPDPS '03. Washington DC USA: IEEE Computer Society 2003 pp. 289.2-.
P. J. Drongowski An introduction to analysis and optimization with AMD CodeAnalyst Performance Analyzer September 2008.
F. Bellosa and M. Steckermeier "The performance implications of locality information usage in shared-memory multiprocessors " Journal of Parallel Distributed Computing vol. 37 pp. 113-121 August 1996. (Pubitemid 126167771)
B. Weissman "Performance counters and state sharing annotations: a unified approach to thread locality " SIG. Operat. Sys. Rev. vol. 32 pp. 127-138 October 1998.
D. Tam R. Azimi and M. Stumm "Thread clustering: sharing-aware scheduling on smp-cmp-smt multiprocessors " SIG. Operat. Sys. Rev. vol. 41 pp. 47-58 March 2007. (Pubitemid 47281574)
R. West P. Zaroo C. A. Waldspurger and X. Zhang "Online cache modeling for commodity multicore processors " SIGOPS Ope. Sys. Rev. vol. 44 pp. 19-29 December 2010.
J. M. Calandrino and J. H. Anderson "On the design and implementation of a cache-aware multicore real-time scheduler " in Proc. of the 21st Euromicro Conference on Real-Time Systems Washington DC USA 2009 pp. 194-204.
Publicado
07/11/2011
Como Citar
GRACIOLI, Giovani; FROHLICH, Antonio.
API para Monitoramento de Desempenho em Sistemas Multicore Embarcados. In: SIMPÓSIO BRASILEIRO DE ENGENHARIA DE SISTEMAS COMPUTACIONAIS (SBESC), 1. , 2011, Florianópolis.
Anais [...].
Porto Alegre: Sociedade Brasileira de Computação,
2011
.
p. 194-199.
ISSN 2237-5430.
