Implementation and Analysis of a Low-Power Heart Rate Prediction Solution Using Hardware Acceleration on the ESP32-S3 Microcontroller

  • João P. M. Clevelares UFES
  • Higor D. Oliveira UFES
  • André G. C. Pacheco UFES
  • Luis A. Souza Jr UFES
  • Rodolfo S. Villaça UFES

Resumo


This work details the implementation of an accelerometry-based heart-rate estimation system optimized for the ESP32-S3 microcontroller. It leverages PIE-based Single Instruction, Multiple Data (SIMD) extensions via ESP-DSP library to accelerate the pre-processing, training and inference of a continual-learning model. Under a modular FreeRTOS architecture, the system achieved 4.99 µs training latency, requiring less than 1 kB of RAM for the ML model itself. Results show a 30.6% computational performance gain and 8% energy consumption reduction with acceleration enabled. These efficiencies allow race-to-sleep strategies that extend the estimated battery life to 51 days on COTS hardware.

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Publicado
19/07/2026
CLEVELARES, João P. M.; OLIVEIRA, Higor D.; PACHECO, André G. C.; SOUZA JR, Luis A.; VILLAÇA, Rodolfo S.. Implementation and Analysis of a Low-Power Heart Rate Prediction Solution Using Hardware Acceleration on the ESP32-S3 Microcontroller. In: SEMINÁRIO INTEGRADO DE SOFTWARE E HARDWARE (SEMISH), 53. , 2026, Gramado/RS. Anais [...]. Porto Alegre: Sociedade Brasileira de Computação, 2026 . p. 388-399. ISSN 2595-6205. DOI: https://doi.org/10.5753/semish.2026.21854.