Simulação de Arquiteturas de Hardware com Memórias Não-Voláteis
Resumo
As novas tecnologias de memórias não voláteis, conhecidas coletivamente como NVMs, prometem rivalizar com a DRAM na disputa pela escolha da tecnologia da memória principal. As NVMs possibilitam, por exemplo, a manipulação de dados persistentes sem o uso de cópias transientes das mesmas. Apesar disso as NVMs ainda não são capazes de oferecer um desempenho superior à DRAM. Levando isso em consideração, a configuração onde se usa uma memória principal híbrida, composta da tradicional DRAM e de NVMs auxiliando na manipulação de dados persistentes, se torna uma solução interessante. Este artigo descreve um simulador que é capaz de simular um sistema onde a memória principal é composta por uma ou mais tecnologias distintas. Utilizamos o simulador para comparar a substituição total de DRAM por NVMs e mostramos que atualmente isso levaria à uma considerável perda de desempenho. Também descrevemos uma API que é capaz de fazer uso de NVM, focando no caso da memória híbrida, onde demonstramos as possibilidades que podem ser melhor exploradas.Referências
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Binkert, N., Beckmann, B., Black, G., Reinhardt, S. K., Saidi, A., Basu, A., Hestness, J., Hower, D. R., Krishna, T., Sardashti, S., Sen, R., Sewell, K., Shoaib, M., Vaish, N., Hill, M. D., and Wood, D. A. (2011). The gem5 simulator. SIGARCH Comput. Archit. News, 39(2):1–7.
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Choi, Y., Song, I., Park, M.-H., Chung, H., Chang, S., Cho, B., Kim, J., Oh, Y., Kwon, D., Sunwoo, J., et al. (2012). A 20nm 1.8 v 8gb pram with 40mb/s In Solid-State Circuits Conference Digest of Technical Papers program bandwidth. (ISSCC), 2012 IEEE International, pages 46–48. IEEE.
Coburn, J., Cauleld, A. M., Akel, A., Grupp, L. M., Gupta, R. K., Jhala, R., and Swanson, S. (2011). NV-Heaps: Making Persistent Objects Fast and Safe with Next-generation, Non-volatile Memories. In Proceedings of the Sixteenth International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS XVI, pages 105–118, New York, NY, USA. ACM.
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McCalpin, J. D. (1995). Memory bandwidth and machine balance in current high performance computers. IEEE Computer Society Technical Committee on Computer Architecture (TCCA) Newsletter, pages 19–25.
Narayanan, D. and Hodson, O. (2012). Whole-system per sistence. ACM SIGARCH Computer Architecture News, 40(1):401–410.
Patel, A., Afram, F., and Ghose, K. (2011). Marss-x86: A qemu-based micro-architectural and systems simulator for x86 multicore processors. In 1st International Qemu Users' Forum, pages 29–30.
Poremba, M., Zhang, T., and Xie, Y. (2015). Nvmain 2.0: A userfriendly memory simulator to model (non-)volatile memory systems. IEEE Computer Architecture Letters, 14(2):140–143.
Ren, J., Zhao, J., Khan, S., Choi, J., Wu, Y., and Mutlu, O. (2015). Thynvm: enabling software-transparent crash consistency in persistent memory systems. In Proceedings of the 48th International Symposium on Microarchitecture, pages 672–685. ACM.
Sanchez, D. and Kozyrakis, C. (2013). Zsim: Fast and accurate microarchitectural simulation of thousand-core systems. SIGARCH Comput. Archit. News, 41(3):475–486.
Schmidt, J. W. (1977). Some high level language constructs for data of type relation. ACM Transactions on Database Systems (TODS), 2(3):247–261.
Tevanian, A., Rashid, R. F., Young, M., Golub, D. B., Thompson, M. R., Bolosky, W. J., and Sanzi, R. (1987). A unix interface for shared memory and memory mapped les under mach. In USENIX Summer, pages 53–68.
Volos, H., Tack, A. J., and Swift, M. M. (2011). Mnemosyne: Lightweight Persistent Memory. In Proceedings of the Sixteenth International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS XVI, pages 91–104, New York, NY, USA. ACM.
Wilcox, M. (2014). DAX: Page cache bypass for lesystems on memory storage. Linux Kernel Mailing List. https://lwn.net/Articles/618064/.
Yi, J. and Lilja, D. (2006). Simulation of computer architectures: simulators, benchmarks, methodologies, and recommendations. Computers, IEEE Transactions on, 55(3):268–280.
Zhao, J., Li, S., Yoon, D. H., Xie, Y., and Jouppi, N. P. (2013). Kiln: Closing the performance gap between systems with and without persistence support. In Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture, pages 421–432. ACM.
(2015). LIBNVDIMM: Non-Volatile Devices v13. https://www.kernel.org/doc/Documentation/nvdimm/nvdimm.txt.
(2016). AXLE project: Advanced analytics for extremely large european data bases. https://axleproject.eu/.
Atkinson, M. P., Daynes, L., Jordan, M. J., Printezis, T., and Spence, S. (1996). An orthogonally persistent java. ACM Sigmod Record, 25(4):68–75.
Binkert, N., Beckmann, B., Black, G., Reinhardt, S. K., Saidi, A., Basu, A., Hestness, J., Hower, D. R., Krishna, T., Sardashti, S., Sen, R., Sewell, K., Shoaib, M., Vaish, N., Hill, M. D., and Wood, D. A. (2011). The gem5 simulator. SIGARCH Comput. Archit. News, 39(2):1–7.
Chakrabarti, D. R., Boehm, H.-J., and Bhandari, K. (2014). Atlas: In Proceedings of the 2014 Leveraging locks for non-volatile memory consistency. ACM International Conference on Object Oriented Programming Systems Languages & Applications, OOPSLA '14, pages 433–452, New York, NY, USA. ACM.
Choi, Y., Song, I., Park, M.-H., Chung, H., Chang, S., Cho, B., Kim, J., Oh, Y., Kwon, D., Sunwoo, J., et al. (2012). A 20nm 1.8 v 8gb pram with 40mb/s In Solid-State Circuits Conference Digest of Technical Papers program bandwidth. (ISSCC), 2012 IEEE International, pages 46–48. IEEE.
Coburn, J., Cauleld, A. M., Akel, A., Grupp, L. M., Gupta, R. K., Jhala, R., and Swanson, S. (2011). NV-Heaps: Making Persistent Objects Fast and Safe with Next-generation, Non-volatile Memories. In Proceedings of the Sixteenth International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS XVI, pages 105–118, New York, NY, USA. ACM.
Greengard, S. (2015). Better memory. Communications of the ACM, 59(1):23–25.
Huan, J., Badam, A., Qureshi, M. K., and Schwann, K. (2015). Unied Address Translation for Memory-Mapped SSDs with FlashMap. In International Symposium on Computer Architecture (ISCA'15).
Intel (2015). The NVM library. http://pmem.io/.
Jung, J.-Y. and Cho, S. (2013). Memorage: Emerging persistent ram based malleable main memory and storage architecture. In Proceedings of the 27th international ACM conference on International conference on supercomputing, pages 115–126. ACM.
Kannan, S., Gavrilovska, A., and Schwan, K. (2016). pvm: persistent virtual memory for efcient capacity scaling and object storage. In Proceedings of the Eleventh European Conference on Computer Systems, page 13. ACM.
Kawahara, A., Azuma, R., Ikeda, Y., Kawai, K., Katoh, Y., Tanabe, K., Nakamura, T., Sumimoto, Y., Yamada, N., Nakai, N., Sakamoto, S., Hayakawa, Y., Tsuji, K., Yoneda, S., Himeno, A., i. Origasa, K., Shimakawa, K., Takagi, T., Mikawa, T., and Aono, K. (2012). An 8mb multi-layered cross-point reram macro with 443mb/s write throughput. In 2012 IEEE International Solid-State Circuits Conference, pages 432–434.
Litzkow, M. J., Livny, M., and Mutka, M. W. (1988). Condor-a hunter of idle workstations. In Distributed Computing Systems, 1988., 8th International Conference on, pages 104–111. IEEE.
Liu, R.-S., Shen, D.-Y., Yang, C.-L., Yu, S.-C., and Wang, C.-Y. M. (2014). Nvm duet: Unied working memory and persistent store architecture. In ACM SIGPLAN Notices, volume 49, pages 455–470. ACM.
Luk, C.-K., Cohn, R., Muth, R., Patil, H., Klauser, A., Lowney, G., Wallace, S., Reddi, V. J., and Hazelwood, K. (2005). Pin: Building customized program analysis tools with dynamic instrumentation. SIGPLAN Not., 40(6):190–200.
McCalpin, J. D. (1995). Memory bandwidth and machine balance in current high performance computers. IEEE Computer Society Technical Committee on Computer Architecture (TCCA) Newsletter, pages 19–25.
Narayanan, D. and Hodson, O. (2012). Whole-system per sistence. ACM SIGARCH Computer Architecture News, 40(1):401–410.
Patel, A., Afram, F., and Ghose, K. (2011). Marss-x86: A qemu-based micro-architectural and systems simulator for x86 multicore processors. In 1st International Qemu Users' Forum, pages 29–30.
Poremba, M., Zhang, T., and Xie, Y. (2015). Nvmain 2.0: A userfriendly memory simulator to model (non-)volatile memory systems. IEEE Computer Architecture Letters, 14(2):140–143.
Ren, J., Zhao, J., Khan, S., Choi, J., Wu, Y., and Mutlu, O. (2015). Thynvm: enabling software-transparent crash consistency in persistent memory systems. In Proceedings of the 48th International Symposium on Microarchitecture, pages 672–685. ACM.
Sanchez, D. and Kozyrakis, C. (2013). Zsim: Fast and accurate microarchitectural simulation of thousand-core systems. SIGARCH Comput. Archit. News, 41(3):475–486.
Schmidt, J. W. (1977). Some high level language constructs for data of type relation. ACM Transactions on Database Systems (TODS), 2(3):247–261.
Tevanian, A., Rashid, R. F., Young, M., Golub, D. B., Thompson, M. R., Bolosky, W. J., and Sanzi, R. (1987). A unix interface for shared memory and memory mapped les under mach. In USENIX Summer, pages 53–68.
Volos, H., Tack, A. J., and Swift, M. M. (2011). Mnemosyne: Lightweight Persistent Memory. In Proceedings of the Sixteenth International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS XVI, pages 91–104, New York, NY, USA. ACM.
Wilcox, M. (2014). DAX: Page cache bypass for lesystems on memory storage. Linux Kernel Mailing List. https://lwn.net/Articles/618064/.
Yi, J. and Lilja, D. (2006). Simulation of computer architectures: simulators, benchmarks, methodologies, and recommendations. Computers, IEEE Transactions on, 55(3):268–280.
Zhao, J., Li, S., Yoon, D. H., Xie, Y., and Jouppi, N. P. (2013). Kiln: Closing the performance gap between systems with and without persistence support. In Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture, pages 421–432. ACM.
Publicado
05/10/2016
Como Citar
PALMA, Mauricio; FRANCESQUINI, Emilio; AZEVEDO, Rodolfo.
Simulação de Arquiteturas de Hardware com Memórias Não-Voláteis. In: SIMPÓSIO EM SISTEMAS COMPUTACIONAIS DE ALTO DESEMPENHO (SSCAD), 17. , 2016, Aracajú.
Anais [...].
Porto Alegre: Sociedade Brasileira de Computação,
2016
.
p. 121-132.
DOI: https://doi.org/10.5753/wscad.2016.14253.