Identificação Automática de Dark Silicon em Processadores Multicore

• Ana Caroline Silva UFMS
• Tony Bignardi UFMS / IFMS
• Edilson de Palma UFMS
• Rafael Alves UFMS
• Clara Hayashi UFMS
• Ricardo Santos UFMS

DOI: https://doi.org/10.5753/wscad.2015.14275

Abstract

Currently, modern processor designs have reduced the chip area that can work on maximum clock frequency to sustain the performance levels according to the Moore's law. On this regime, the chip area which should stay on low frequency is named dark silicon. Since dark silicon is dependent on the technological process, modern processor designs should identify the dark silicon area to explore architectural resources to mitigate it. This work focuses on the dark silicon identification and area estimates by using a multicore design tool named MultiExplorer. We have evaluated the MultiExplorer dark silicon estimates from a set of Intel Pentium multicore processors built on transistors technologies from 90nm up to 22nm.

References

Allred, J. M. (2013). Designing, optimizing, and sustaining heterogeneous chip multiprocessors to systematically exploit dark silicon. PhD thesis, UTAH STATE UNIVERSITY.

Borkar, S. (1999). Design challenges of technology scaling. Micro, IEEE, 19(4):23–29.

Borkar, S. (2009). Design perspectives on 22nm cmos and beyond. In Proceedings of the 46th Annual Design Automation Conference, pages 93–94. ACM.

Devigo, R., Duenha, L., Azevedo, R., and Santos, R. (2015). Multiexplorer: A tool set for multicore system-on-chip design exploration. In Proceedings of the 26th International Conference on Application-specic, Systems, Architectures and Processors. IEEE.

Duenha, L., Guedes, M., Almeida, H., Boy, M., and Azevedo, R. (2014). Mpsocbench: A toolset for mpsoc system level evaluation. In International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS), pages 164– 171. IEEE.

Esmaeilzadeh, H., Blem, E., Amant, R. S., Sankaralingam, K., and Burger, D. (2012). Dark silicon and the end of multicore scaling. IEEE Micro, (3):122–134.

Hardavellas, N., Ferdman, M., Falsa, B., and Ailamaki, A. (2011). Toward dark silicon in servers. IEEE Micro, 31(EPFL-ARTICLE-168285):6–15.

Li, S., Ahn, J. H., Strong, R. D., Brockman, J. B., Tullsen, D. M., and Jouppi, N. P. (2009). Mcpat: an integrated power, area, and timing modeling framework for multicore and manycore architectures. In Microarchitecture, 2009. MICRO-42. 42nd Annual IEEE/ACM International Symposium on, pages 469–480. IEEE.

Nathan Goulding-Hotta, Jack Sampson, G. V. S. G. J. A. P.-C. H. M. A. S. N. V. B. J. B. S. S. e. M. B. l. (2011). The greendroid mobile application processor: An architecture for silicon's dark future. IEEE Micro, 31(2):86–95.

Robert H. Dennard, Fritz H. Gaensslen, H. n. Y. V. L. R.-E. B. A. and Leblanc, R. (1974). Design of ion-implanted mosfets with very small physical dimensions. IEEE Journal of Solid-Circuits, pages 256–267.

Schaller, R. R. (1997). Moore's law: Paste, present and future. IEEE Spectrum, 34(6):52–59.

Ubal, R., Jang, B., Mistry, P., Schaa, D., and Kaeli, D. (2012). Multi2sim: a simulation framework for cpu-gpu computing. In Proceedings of the 21st international conference on Parallel architectures and compilation techniques, pages 335–344. ACM.

Ubal, R., Sahuquillo, J., Petit, S., and Lopez, P. (2007). Multi2sim: A simulation framework to evaluate multicore-multithreaded processors. In International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD), pages 62– 68.

Venkatesh, G., Sampson, J., Goulding, N., Garcia, S., Bryksin, V., Lugo-Martinez, J., Swanson, S., and Taylor, M. B. (2010). Conservation cores: reducing the energy of mature computations. In ACM SIGARCH Computer Architecture News, volume 38, pages 205–218. ACM.