Reavaliando a Eficiência Energética de Memória Transacional em Processadores Convencionais
Resumo
Memória Transacional (TM) é um mecanismo recente de sincronização que objetiva ao mesmo tempo facilitar o desenvolvimento de aplicações concorrentes e fornecer desempenho. A maioria dos trabalhos em TM focam avaliação de desempenho, negligenciando outras métricas como consumo de energia. Trabalhos anteriores analisaram a eficiência energética de implementações de TM através de ambientes simulados com modelo de execução simplificado. Este trabalho apresenta uma reavaliação do consumo de energia e desempenho de uma implementação moderna de memória transacional em processadores convencionais. Será descrito e discutido uma técnica de medição de energia baseada em Registradores Específicos de Modelo (MSRs), técnica essa utilizada para obter e analisar o consumo energético de aplicações transacionais do benchmark STAMP, bem como de suas respectivas implementações baseadas em travas. Também será discutido o comportamento do consumo de energia e desempenho devido à influência de diferentes gerenciados de frequência disponíveis em configurações típicas de sistemas Linux. Nossos resultados mostram que memória transacional em software de fato reduz o consumo de energia quando comparada a implementações baseadas em travas grossas em 7 das 8 aplicações estudadas em um processador Intel® Sandy Bridge™.
Palavras-chave:
Programação concorrente, Análise de desempenho e energia, Memória Transacional
Referências
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H. Lien, L. Natvig, A. A. Hasib, and J. C. Meyer, “Case studies of multi-core energy efficiency in task based programs,” in ICT as Key Technology Against Global Warming, ser. Lecture Notes in Computer Science. Springer Berlin Heidelberg, 2012, vol. 7453, pp. 44–54.
J. M. Cebrian, L. Natvig, and J. C. Meyer, “Improving energy efficiency through parallelization and vectorization on Intel Core i5 and i7 processors,” in Proceedings of the 2012 SC Companion: High Performance Computing, Networking Storage and Analysis, Nov. 2012, pp. 675–684.
M. Hähnel, B. Döbel, M. Völp, and H. Härtig, “Measuring energy consumption for short code paths using RAPL,” ACM SIGMETRICS Performance Evaluation Review, vol. 40, no. 3, pp. 13–17, Jan. 2012.
T. Moreshet, R. I. Bahar, and M. Herlihy, “Energy reduction in multiprocessor systems using transactional memory,” in Proceedings of the 2005 international symposium on Low power electronics and design, Aug. 2005, pp. 331–334.
C. Ferri, S. Wood, T. Moreshet, R. I. Bahar, and M. Herlihy, “Embedded-TM: Energy and complexity-effective hardware transactional memory for embedded multicore systems,” Journal of Parallel and Distributed Computing, vol. 70, no. 10, pp. 1042–1052, Oct. 2010.
F. Klein, A. Baldassin, G. Araujo, P. Centoducatte, and R. Azevedo, “On the energy-efficiency of software transactional memory,” in Proceedings of the 22nd Annual Symposium on Integrated Circuits and System Design, Sep. 2009, pp. 1–6.
A. Baldassin, F. Klein, G. Araujo, R. Azevedo, and P. Centoducatte, “Characterizing the energy consumption of software transactional memory,” IEEE Computer Architecture Letters, vol. 8, no. 2, pp. 56–59, 2009.
A. Baldassin, J. P. L. de Carvalho, L. A. G. Garcia, and R. Azevedo, “Energy-performance tradeoffs in software transactional memory,” in Proceedings of the 2012 IEEE 24th International Symposium on Computer Architecture and High Performance Computing, 2012, pp. 147–154.
T. M. Rico, M. L. Pilla, and A. R. D. Bois, “Energy consumption on software transactional memories,” in Anais do Simposio em Sistemas Computacionais, Oct. 2012, pp. 194–201.
A. Gautham, K. Korgaonkar, P. Slpsk, S. Balachandran, and K. Veezhinathan, “The implications of shared data synchronization techniques on multi-core energy efficiency,” in Proceedings of the 2012 Workshop on Power-Aware Computing and Systems, Oct. 2012, p. 6.
T. Harris, J. Larus, and R. Rajwar, Transactional Memory, 2nd ed. Morgan & Claypool Publishers, Jun. 2010.
A. Wang, M. Gaudet, P. Wu, J. N. Amaral, M. Ohmacht, C. Barton, R. Silvera, and M. Michael, “Evaluation of Blue Gene/Q hardware support for transactional memories,” in Proceedings of the 21st International Conference on Parallel Architectures and Compilation Techniques, Sep. 2012, pp. 127–136.
Intel R Architecture Instruction Set Extensions Programming Reference, Intel Corporation, Feb. 2012.
L. A. Barroso and U. Holzle, “The case for energyproportional computing,” IEEE Computer, vol. 40, no. 12, pp. 33–37, Dec. 2007.
N. Firasta, M. Buxton, K. Nasri, and S. Kuo, Intel R AVX: New Frontiers in Performance Improvements and Energy Efficiency, May 2008.
P. Larsson, Intel R Energy-Efficient Software Guidelines, June 2012.
H. David, E. Gorbatov, U. R. Hanebutte, R. Khanna, and C. Le, “RAPL: memory power estimation and capping,” in Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design, 2010, pp. 189–194.
C. C. Minh, J. Chung, C. Kozyrakis, and K. Olukotun, “STAMP: Stanford Transactional Applications for Multi- Processing,” in Proceedings of the IEEE International Symposium on Workload Characterization, Sep. 2008, pp. 35–46.
P. Felber, C. Fetzer, and T. Riegel, “Dynamic performance tuning of word-based software transactional memory,” in Proceedings of the 13th Symposium on Principles and Practice of Parallel Programming, Feb. 2008, pp. 237–246.
K. P. Eswaran, J. N. Gray, R. A. Lorie, and I. L. Traiger, “The notions of consistency and predicate locks in a database system,” Communications of the ACM, vol. 19, no. 11, pp. 624–633, Nov. 1976.
D. B. Lomet, “Process structuring, synchronization, and recovery using atomic actions,” in Proceedings of an ACM conference on Language design for reliable software, Mar. 1977, pp. 128–137.
M. Herlihy and J. E. B. Moss, “Transactional memory: Architectural support for lock-free data structures,” in Proceedings of the 20th Annual International Symposium on Computer Architecture, Jun. 1993, pp. 289–300.
Intel R 64 and IA-32 Architectures Software Developer’s Manual, Jan 2013, vol. 3B.
H. Lien, L. Natvig, A. A. Hasib, and J. C. Meyer, “Case studies of multi-core energy efficiency in task based programs,” in ICT as Key Technology Against Global Warming, ser. Lecture Notes in Computer Science. Springer Berlin Heidelberg, 2012, vol. 7453, pp. 44–54.
J. M. Cebrian, L. Natvig, and J. C. Meyer, “Improving energy efficiency through parallelization and vectorization on Intel Core i5 and i7 processors,” in Proceedings of the 2012 SC Companion: High Performance Computing, Networking Storage and Analysis, Nov. 2012, pp. 675–684.
M. Hähnel, B. Döbel, M. Völp, and H. Härtig, “Measuring energy consumption for short code paths using RAPL,” ACM SIGMETRICS Performance Evaluation Review, vol. 40, no. 3, pp. 13–17, Jan. 2012.
T. Moreshet, R. I. Bahar, and M. Herlihy, “Energy reduction in multiprocessor systems using transactional memory,” in Proceedings of the 2005 international symposium on Low power electronics and design, Aug. 2005, pp. 331–334.
C. Ferri, S. Wood, T. Moreshet, R. I. Bahar, and M. Herlihy, “Embedded-TM: Energy and complexity-effective hardware transactional memory for embedded multicore systems,” Journal of Parallel and Distributed Computing, vol. 70, no. 10, pp. 1042–1052, Oct. 2010.
F. Klein, A. Baldassin, G. Araujo, P. Centoducatte, and R. Azevedo, “On the energy-efficiency of software transactional memory,” in Proceedings of the 22nd Annual Symposium on Integrated Circuits and System Design, Sep. 2009, pp. 1–6.
A. Baldassin, F. Klein, G. Araujo, R. Azevedo, and P. Centoducatte, “Characterizing the energy consumption of software transactional memory,” IEEE Computer Architecture Letters, vol. 8, no. 2, pp. 56–59, 2009.
A. Baldassin, J. P. L. de Carvalho, L. A. G. Garcia, and R. Azevedo, “Energy-performance tradeoffs in software transactional memory,” in Proceedings of the 2012 IEEE 24th International Symposium on Computer Architecture and High Performance Computing, 2012, pp. 147–154.
T. M. Rico, M. L. Pilla, and A. R. D. Bois, “Energy consumption on software transactional memories,” in Anais do Simposio em Sistemas Computacionais, Oct. 2012, pp. 194–201.
A. Gautham, K. Korgaonkar, P. Slpsk, S. Balachandran, and K. Veezhinathan, “The implications of shared data synchronization techniques on multi-core energy efficiency,” in Proceedings of the 2012 Workshop on Power-Aware Computing and Systems, Oct. 2012, p. 6.
Publicado
23/10/2013
Como Citar
CARVALHO, João P. L. de; BALDASSIN, Alexandro; AZEVEDO, Rodolfo.
Reavaliando a Eficiência Energética de Memória Transacional em Processadores Convencionais. In: SIMPÓSIO EM SISTEMAS COMPUTACIONAIS DE ALTO DESEMPENHO (SSCAD), 14. , 2013, Porto de Galinhas.
Anais [...].
Porto Alegre: Sociedade Brasileira de Computação,
2013
.
p. 69-76.
DOI: https://doi.org/10.5753/wscad.2013.16775.
