DTSD: Uma Arquitetura com Mecanismo Híbrido de Execução
Resumo
Este trabalho apresenta a Dynamically Trace Scheduling Dataflow (DTSD), uma arquitetura híbrida que executa código em dois modos distintos: de fluxo de controle e de fluxo de dados (control-flow/dataflow). Máquinas DTSD incluem: um processador primário que executa instruções escalares de forma tradicional (fluxo de controle); uma unidade que traduz dinamicamente trechos de código escalar em blocos de instruções Explicit Data Graph Execution; e um processador Dataflow que executa estes blocos segundo o fluxo de dados. Esta nova arquitetura foi avaliada experimentalmente: implementamos um simulador DTSD com substrato Simplescalar, e empregamos um ambiente de simulação da arquitetura Super Escalar Alpha 21264 em análise comparativa. Nossos resultados experimentais mostraram que, em média, o desempenho da arquitetura DTSD supera o de uma Super Escalar equivalente em 183%.
Referências
M. Johnson, "Superscalar Microprocessor Design", Prentice-Hall, 1991.
E. Rotenberg, S. Benneu, and J. E. Smith, 'Trace Cache: A Low Latency Approach to High Bandwidth lnstruction Fetching", Proc. 29th Annual Intemational Symposium on Microarchitecture, p. 24-34, 1996.
D. W. Wall, "Limits of Instruction-Level Parallelism", Digital Westem Research Laboratory - WRL Research Report 93/6, November 1993.
D. Burger, S. W. Keckler, K. S. McKinley, M. Dahlin, L. K. John, C. Lin, C. R. Moore, J. Burrill, R. G. McDonald, and W. Yoder, "Scaling to the End of Silicon with EDGE Architectures", IEEE Computer, Vol. 37, No. 7, p. 44-55, July 2004.
A. L. Davis, "A Data Aow Evaluation System Based on the Concept of Recursive Locality", Proc. National Computing Conference, AFIPS Press, Reston, Va., pp. 1079-1086, 1979.
A. H. Vcen, "Oataflow Machine Arc hitecture", ACM Computing Surveys, Vol. 18, No. 4, pp. 335-396, December 1986.
A. F. De Souza and P. Rounce, "Dynamically Trace Schcdulcd VLIW Architectures", in Lecture Notes in Computer Science, Vol. 140 I, p. 993-995, 1998.
A. F. De Souza and P. Rounce, "Dynamically Scheduling VLIW Instructions", Journal of Parallel and Distributcd Computing, Vol. 60, No. 12, p. 1480-1511, December 2000.
T. Austin and D. Burger, "The SimpleScalar Tool Set", Technical Report TR-1342, Computer Science Department, University of Wisconsin - Madison, June 1997.
Compaq Computer Corporation, "Aipha 21264 Microprocessor Hardware Reference Manual", Compaq Computer Corporation, 1999.
F. L. L Almeida, "Escalonamento Dinâmico de Caminhos de Execução em Blocos de Instruções Dataflow", Dissertação de Mestrado, Programa de Pós-Graduação em Informática - UFES, 2007.
W. W. Hwu and Y. N. Pau, "Checkpoint Repair for Out-of-order Execution Machine.". Proc. 14th Annual lntemational Symposium on Computer Architecture, pp. 18-26, 1987.
R. Desikan, D. Burger, and S. W. Keckler, "Measuring Experimental Error in Microprocessor Simulation", Proc. 28th Annual lntemational Symposium on Computer Architecture, pp. 226-277, 2001.
Intel Corporation, "Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume I: Basic Architecture", Intel Corporation, 2008.
E. Horowitz and S. Sahni, "Fundamentais of Computer Algorithms", Computer Science Press Inc., 1978.
D. Knuth, "Art of Computer Programming", AddisonWesley Publishing Co., USA, 1973.
G. Forsythe e C. B. Moler, "Computer Solution of Linear Algebraic Systems", Prentice Hall, Englewood Cliffs, New Jersey, 1967.
F. H. McMahon, "Fortran Kernels: MFLOPS", Lawrence Livermore National Laboratory, 1983.
S. D.. Conte, "Elementary Numerical Analysis", McGraw-Hill Book Co., 1965.
R. Nair and E. M. Hopkins, "Exploiting Instructions Levei Parallelism in Processors by Caching Schcdulcd Groups", Proc. 24th Annual lnternational Symposium on Computer Architecture, pp. l3-25, 1997.
S. C. Santana and A. F. De Souza, "A Comparative Analysis Between EPIC Static Instruction Scheduling and DTSVLIW Dynamic Instruction Scheduling", Workshop on Exploring the Trace Space for Dynamic Optimization Techniques. pp. 59-67, 2003.
E. Rotenberg, S. Benneu, and J. E. Smith, 'Trace Cache: A Low Latency Approach to High Bandwidth lnstruction Fetching", Proc. 29th Annual Intemational Symposium on Microarchitecture, p. 24-34, 1996.
D. W. Wall, "Limits of Instruction-Level Parallelism", Digital Westem Research Laboratory - WRL Research Report 93/6, November 1993.
D. Burger, S. W. Keckler, K. S. McKinley, M. Dahlin, L. K. John, C. Lin, C. R. Moore, J. Burrill, R. G. McDonald, and W. Yoder, "Scaling to the End of Silicon with EDGE Architectures", IEEE Computer, Vol. 37, No. 7, p. 44-55, July 2004.
A. L. Davis, "A Data Aow Evaluation System Based on the Concept of Recursive Locality", Proc. National Computing Conference, AFIPS Press, Reston, Va., pp. 1079-1086, 1979.
A. H. Vcen, "Oataflow Machine Arc hitecture", ACM Computing Surveys, Vol. 18, No. 4, pp. 335-396, December 1986.
A. F. De Souza and P. Rounce, "Dynamically Trace Schcdulcd VLIW Architectures", in Lecture Notes in Computer Science, Vol. 140 I, p. 993-995, 1998.
A. F. De Souza and P. Rounce, "Dynamically Scheduling VLIW Instructions", Journal of Parallel and Distributcd Computing, Vol. 60, No. 12, p. 1480-1511, December 2000.
T. Austin and D. Burger, "The SimpleScalar Tool Set", Technical Report TR-1342, Computer Science Department, University of Wisconsin - Madison, June 1997.
Compaq Computer Corporation, "Aipha 21264 Microprocessor Hardware Reference Manual", Compaq Computer Corporation, 1999.
F. L. L Almeida, "Escalonamento Dinâmico de Caminhos de Execução em Blocos de Instruções Dataflow", Dissertação de Mestrado, Programa de Pós-Graduação em Informática - UFES, 2007.
W. W. Hwu and Y. N. Pau, "Checkpoint Repair for Out-of-order Execution Machine.". Proc. 14th Annual lntemational Symposium on Computer Architecture, pp. 18-26, 1987.
R. Desikan, D. Burger, and S. W. Keckler, "Measuring Experimental Error in Microprocessor Simulation", Proc. 28th Annual lntemational Symposium on Computer Architecture, pp. 226-277, 2001.
Intel Corporation, "Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume I: Basic Architecture", Intel Corporation, 2008.
E. Horowitz and S. Sahni, "Fundamentais of Computer Algorithms", Computer Science Press Inc., 1978.
D. Knuth, "Art of Computer Programming", AddisonWesley Publishing Co., USA, 1973.
G. Forsythe e C. B. Moler, "Computer Solution of Linear Algebraic Systems", Prentice Hall, Englewood Cliffs, New Jersey, 1967.
F. H. McMahon, "Fortran Kernels: MFLOPS", Lawrence Livermore National Laboratory, 1983.
S. D.. Conte, "Elementary Numerical Analysis", McGraw-Hill Book Co., 1965.
R. Nair and E. M. Hopkins, "Exploiting Instructions Levei Parallelism in Processors by Caching Schcdulcd Groups", Proc. 24th Annual lnternational Symposium on Computer Architecture, pp. l3-25, 1997.
S. C. Santana and A. F. De Souza, "A Comparative Analysis Between EPIC Static Instruction Scheduling and DTSVLIW Dynamic Instruction Scheduling", Workshop on Exploring the Trace Space for Dynamic Optimization Techniques. pp. 59-67, 2003.
Publicado
29/10/2008
Como Citar
ALMEIDA, Fernando Líbio Leite; SOUZA, Alberto F. De; FERNANDES, Edil S. T..
DTSD: Uma Arquitetura com Mecanismo Híbrido de Execução. In: SIMPÓSIO EM SISTEMAS COMPUTACIONAIS DE ALTO DESEMPENHO (SSCAD), 9. , 2008, Campo Grande.
Anais [...].
Porto Alegre: Sociedade Brasileira de Computação,
2008
.
p. 45-52.
DOI: https://doi.org/10.5753/wscad.2008.17666.
