Investigação do Uso de Caches com Suporte a Coerência de Dados em Plataformas MPSoC baseadas em NoC
Resumo
Os Multiprocessor System-on-Chip surgem como grande solução para dar suporte a aplicações que exigem um maior poder computacional em um único chip. Nestes sistemas, a coerência e consistência de cache ainda é um assunto em aberto. Este artigo apresenta uma investigação da hierarquia de memória de uma plataforma multiprocessada baseada em Network-on-Chip no que diz respeito ao uso de cache e uma análise das conseqüências do uso de um mecanismo de coerência de cache. São apresentados resultados comparativos entre uma plataforma com cache e uma versão sem cache. Estes resultados dizem respeito à carga injetada na rede durante a execução da aplicação, o tempo de resposta das operações de leitura bem como speedup e eficiência.Referências
ITRS, International technology roadmap for semiconductors update 2003, http://public.itrs.net.
Petrot, F.; Greiner, A.; Gomez, P.; “On Cache Coherency and Memory Consistency Issues in NoC Based Shared Memory Multiprocessor SoC Architectures”. In: Digital System Design: Architectures, Methods and Tools, 2006. DSD 2006. 9th EUROMICRO Conference on 30-01 Aug. 2006 Page(s):53 – 60.
Hwang, K. “Advanced Computer Architecture: Parallelism, Scalability, Programmability”, McGraw- Hill, Inc. 1993.
Benini, L. et al; “MPARM: Exploring the Multi- Processor SoC Design Space with SystemC”. The Journal of VLSI Signal Processing, 41(2): 169 – 182, September 2005.
Fummi, F. et al; “Native ISS-SystemC Integration for Co-Simulation of Multi-Processor SoC”. Design, Automation and Test in Europe (DATE), Proceedings, 2004.
Suh, T.; Blough, D. M.; Lee, H. H. S. “Supporting cache coherence in heterogeneous multiprocessor systems”. Design, Automation and Test in Europe Conference and Exhibition, 2004. Proceedings Volume 2, 16-20 Feb. 2004 Page(s):1150 - 1155 Vol.2.
Forsell, M. “A scalable high-performance computing solution for network on chip”. IEEE Micro, vol. 22, no. 5, pp. 46–55, Sep.—Oct. 2002.
Paulin, P.; Pilkington, C.; Bensoudane, E. Stepnp: “A system-level exploration platform for network processors”. IEEE Design & Test of Computers, pages 17–26, Nov. 2002.
Salapura, V.; Georgiou, C. J.; Nair, I. “An efficient systemon- a-chip design methodology for networking applications”. In Proc. of the Int’l Conf. on Compilers, Arch. and Synth. Of Embedded Sys., Washington, DC, Sept. 2004.
Kim, D.; Kim, M.; Sobelman, G.E. “DCOS: Cache Embedded Switch Architecture for Distributed Shared Memory Multiprocessor SoCs,” Proceedings, IEEE International Symposium on Circuits and Systems, pp. 979-982, 2006.
Soares, R.; Silva, I.S.; Azevedo, A. “When Reconfigurable Architecture Meets Network-on-Chip”, 17th Symposium on Integrated Circuits and Systems Design, pp. 216 – 221, 2003.
Cho, S.L.; Yang, M.K.; Lee, J.; “Analytical modeling of a fat-tree network with buffered switches”, Communications, Computers and signal Processing, 2001, pp:184 – 187.
Petrot, F.; Greiner, A.; Gomez, P.; “On Cache Coherency and Memory Consistency Issues in NoC Based Shared Memory Multiprocessor SoC Architectures”. In: Digital System Design: Architectures, Methods and Tools, 2006. DSD 2006. 9th EUROMICRO Conference on 30-01 Aug. 2006 Page(s):53 – 60.
Hwang, K. “Advanced Computer Architecture: Parallelism, Scalability, Programmability”, McGraw- Hill, Inc. 1993.
Benini, L. et al; “MPARM: Exploring the Multi- Processor SoC Design Space with SystemC”. The Journal of VLSI Signal Processing, 41(2): 169 – 182, September 2005.
Fummi, F. et al; “Native ISS-SystemC Integration for Co-Simulation of Multi-Processor SoC”. Design, Automation and Test in Europe (DATE), Proceedings, 2004.
Suh, T.; Blough, D. M.; Lee, H. H. S. “Supporting cache coherence in heterogeneous multiprocessor systems”. Design, Automation and Test in Europe Conference and Exhibition, 2004. Proceedings Volume 2, 16-20 Feb. 2004 Page(s):1150 - 1155 Vol.2.
Forsell, M. “A scalable high-performance computing solution for network on chip”. IEEE Micro, vol. 22, no. 5, pp. 46–55, Sep.—Oct. 2002.
Paulin, P.; Pilkington, C.; Bensoudane, E. Stepnp: “A system-level exploration platform for network processors”. IEEE Design & Test of Computers, pages 17–26, Nov. 2002.
Salapura, V.; Georgiou, C. J.; Nair, I. “An efficient systemon- a-chip design methodology for networking applications”. In Proc. of the Int’l Conf. on Compilers, Arch. and Synth. Of Embedded Sys., Washington, DC, Sept. 2004.
Kim, D.; Kim, M.; Sobelman, G.E. “DCOS: Cache Embedded Switch Architecture for Distributed Shared Memory Multiprocessor SoCs,” Proceedings, IEEE International Symposium on Circuits and Systems, pp. 979-982, 2006.
Soares, R.; Silva, I.S.; Azevedo, A. “When Reconfigurable Architecture Meets Network-on-Chip”, 17th Symposium on Integrated Circuits and Systems Design, pp. 216 – 221, 2003.
Cho, S.L.; Yang, M.K.; Lee, J.; “Analytical modeling of a fat-tree network with buffered switches”, Communications, Computers and signal Processing, 2001, pp:184 – 187.
Publicado
24/10/2007
Como Citar
GIRÃO, Gustavo; OLIVEIRA, Bruno Cruz de; SOARES, Rodrigo; SILVA, Ivan Saraiva.
Investigação do Uso de Caches com Suporte a Coerência de Dados em Plataformas MPSoC baseadas em NoC . In: SIMPÓSIO EM SISTEMAS COMPUTACIONAIS DE ALTO DESEMPENHO (SSCAD), 8. , 2007, Gramado.
Anais [...].
Porto Alegre: Sociedade Brasileira de Computação,
2007
.
p. 33-40.
DOI: https://doi.org/10.5753/wscad.2007.18750.
