O Efeito da Latência no Desempenho da Arquitetura DTSVLIW
Resumo
Neste trabalho apresentamos resultados experimentais que mostram o forte impacto da latência das instruções e da hierarquia da memória no desempenho da arquitetura DTSVLIW. A latência das instruções reduz o desempenho DTSVLIW quando executando programas inteiros do SPEC2000 em 32.0% e, surpreendentemente, em apenas 6.2% no caso de programas de ponto flutuante, muito embora os últimos requeiram a execução de um número muito maior de instruções com altas latências. A latência da hierarquia de memória tem um forte impacto no desempenho da DTSVLIW para programas inteiros - redução de 22,1% - mas ainda maior para programas de ponto flutuante - redução de 85.5%. Estes resultados sugerem trabalhos futuros em técnicas para redução do impacto da latência no desempenho DTSVLIW.
Referências
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S. Davidson, D. Landskov. B. D. Shriver, and P. W. Mallett. "Some Experiments in Local Microcode Compaction for Horizontal Machines", IEEE Transactions on Computers, Vol. C-30, No. 7, pp. 460-477, July 1981.
R. Desikan, D. Burger, and S. W. Keckler, "Measuring Experimental Error in Microprocessor Simulation", Proceedings of the 28th Annual International Symposium on Computer Architecture. pp. 226-277, 2001.
A. F. de Souza and P. Rounce, "Dynamically Scheduling the Trace Produced during Program Execution into VLIW lnstructions", Proceedings of 13th International Parallel Processing Symposium & 10th Symposium on Parallel and Distributed Processing, pp. 248-257, April 1999.
A. F. de Souza, "Integer Performance Evaluation of the Dynamically Trace Scheduled VLIW Architecture", Ph.D. Thesis, Department of Computer Science, University College London, University of London, September 1999.
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A. F. de Souza and P. Rounce. "Dynamically Scheduling VLIW Instructions", Journal of Parallel and Distributed Computing 60, pp. 1480-1511. December 2000.
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Digital Equipment Corporation, "Alpha Architecture Handbook", Digital Equipment Corporation. 1992.
J. A. Fisher, "The VLIW Machine: A Multiprocessor for Compiling Scientific Code", IEEE Computer, pp. 45-5J, July 1984.
B. Jacob and T. Mudge, "Notes on Calculating Computer Performance", Technical Report CSE-TR-231-95. Department of Electrical Engineering and Computer Science, University of Michigan, USA, March 1995.
M. Johnson, "Superscalar Microprocessor Design", Prentice Hall, 1991.
A. J. KleinOsowski and D. J. Lilja, "MinneS PEC: A New SPEC Benchmark Workload for Simulation-Based Computer Architecture Research", Computer Architecture Letters. Volume I, June, 2002.
R. Nair and M. E. Hopkins, "Exploiting lnstructions Levei Parallelism in Processors by Caching Scheduled Groups", Proceedings of the 24th Annual lnternational Symposium on Computer Architecture, pp. 13-25, 1997.
D. A. Patterson and J. L Hennessy, "Computer Architecture: A Quantitative Approach, Third Edition", Morgan Kaufmann Publishers, Inc., 2003.
T. Austin and D. Burger. "The SimpleScalar Tool Set". Technical Report TR-1342. Computer Science Department. University of Wisconsin - Madison. June 1997.
Compaq Computer Corporation. "Alpha 21264 Microprocessor Hardware Reference Manual", Compaq Computer Corporation, 1999.
S. Davidson, D. Landskov. B. D. Shriver, and P. W. Mallett. "Some Experiments in Local Microcode Compaction for Horizontal Machines", IEEE Transactions on Computers, Vol. C-30, No. 7, pp. 460-477, July 1981.
R. Desikan, D. Burger, and S. W. Keckler, "Measuring Experimental Error in Microprocessor Simulation", Proceedings of the 28th Annual International Symposium on Computer Architecture. pp. 226-277, 2001.
A. F. de Souza and P. Rounce, "Dynamically Scheduling the Trace Produced during Program Execution into VLIW lnstructions", Proceedings of 13th International Parallel Processing Symposium & 10th Symposium on Parallel and Distributed Processing, pp. 248-257, April 1999.
A. F. de Souza, "Integer Performance Evaluation of the Dynamically Trace Scheduled VLIW Architecture", Ph.D. Thesis, Department of Computer Science, University College London, University of London, September 1999.
A. F. de Souza and P. Rounce, "Effect of Multicycle Instructions on the Integer Performance of the Dynamically Trace Scheduled VLIW Architecture", on Lecture Notes in Computer Science, V oi. 1593, pp. 1203-1206, 1999.
A. F. de Souza and P. Rounce. "Dynamically Scheduling VLIW Instructions", Journal of Parallel and Distributed Computing 60, pp. 1480-1511. December 2000.
A. F. de Souza and P. Rounce, "Improving the DTSVLIW Performance via Block Compaction", Proceedings of the 13th Symp. on Computer Architecture and High Performance Computing - SBAC-PAD'2001, 2001.
Digital Equipment Corporation, "Alpha Architecture Handbook", Digital Equipment Corporation. 1992.
J. A. Fisher, "The VLIW Machine: A Multiprocessor for Compiling Scientific Code", IEEE Computer, pp. 45-5J, July 1984.
B. Jacob and T. Mudge, "Notes on Calculating Computer Performance", Technical Report CSE-TR-231-95. Department of Electrical Engineering and Computer Science, University of Michigan, USA, March 1995.
M. Johnson, "Superscalar Microprocessor Design", Prentice Hall, 1991.
A. J. KleinOsowski and D. J. Lilja, "MinneS PEC: A New SPEC Benchmark Workload for Simulation-Based Computer Architecture Research", Computer Architecture Letters. Volume I, June, 2002.
R. Nair and M. E. Hopkins, "Exploiting lnstructions Levei Parallelism in Processors by Caching Scheduled Groups", Proceedings of the 24th Annual lnternational Symposium on Computer Architecture, pp. 13-25, 1997.
D. A. Patterson and J. L Hennessy, "Computer Architecture: A Quantitative Approach, Third Edition", Morgan Kaufmann Publishers, Inc., 2003.
Publicado
10/11/2003
Como Citar
ALMEIDA, Fernando Líbio L.; SOUZA, Alberto F. De; FREITAS, Christian Daros de; REIS JR., Neyval Costa.
O Efeito da Latência no Desempenho da Arquitetura DTSVLIW. In: SIMPÓSIO EM SISTEMAS COMPUTACIONAIS DE ALTO DESEMPENHO (SSCAD), 4. , 2003, São Paulo.
Anais [...].
Porto Alegre: Sociedade Brasileira de Computação,
2003
.
p. 64-71.
DOI: https://doi.org/10.5753/wscad.2003.19104.
