ADD - Uma Ferramenta de Projeto de Aceleradores com DataFlow para Alto Desempenho
Resumo
Aceleradores com FPGA baseados em fluxo de dados se tornaram uma alternativa promissora para se conseguir alto desempenho com eficiência energética. Este artigo apresenta a ferramenta ADD (Accelerator Design and Deploy) para descrição de algoritmos com fluxo de dados, que também possibilita a simulação, a prototipação em FPGA e a integração em um ambiente heterogêneo CPU-FPGA. A ferramenta possui uma biblioteca de operadores síncronos, além de possibilitar o desenvolvimento de novos operadores. Oferece suporte para acoplamento com linguagens de programação de alto nível e foi validada na plataforma para computação heterogênea CPU-FPGA de alto desempenho da Intel/Altera. Como resultado, obteve-se ganhos no tempo de processamento dos benchmarks de até seis vezes em relação às execuções single thread, o que mostra a eficiência da ferramenta proposta.
Referências
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Ferreira, R., Cardoso, J. M., and Neto, H. C. (2004). An environment for exploring data-driven architectures. In Int. Conference on Field-Programmable Logic and Applications (FPL).
Ferreira, R., Cardoso, J. M., Toledo, A., and Neto, H. C. (2005). Data-driven regular recongurable arrays: design space exploration and mapping. In Int. Conf. on Embedded Computer Systems Architectures, Modeling and Simulation SAMOS.
Ferreira, R., Nacif, J., Magalhaes, S., de Almeida, T., and Pacico, R. (2015). Be a simulator developer and go beyond in computing engineering. In Frontiers in Education Conference (FIE). IEEE.
Gupta, P. (2016). Accelerating datacenter workloads. In 26th International Conference on Field Programmable Logic and Applications.
Gupta, P. K. (2015). Xeon+ fpga platform for the data center. In Fourth Workshop on the Intersections of Computer Architecture and Recongurable Logic, volume 119.
Hendrich, N. (2000). A java-based framework for simulation and teaching: Hades—the hamburg design system. In Microelectronics Education, pages 285–288. Springer.
IntelFPGA. Intel FPGA Acceleratiing The Smart and Connected World. https: //www.altera.com/. Accessed: 2017-08-09.
Kim, E., Kim, K., and In, H. P. (2010). A multi-view api impact analysis for open spl platform. In Advanced Communication Technology (ICACT), 2010 The 12th International Conference on, volume 1, pages 686–691. IEEE.
Ling, A. C., Aydonat, U., O'Connell, S., Capalija, D., and Chiu, G. R. (2017). Creating high performance applications with intel's fpga openclTM sdk. In Proceedings of the 5th International Workshop on OpenCL, page 11. ACM.
Marwedel, P., Cong, K., and Schwenk, S. (2002). Ravi: Interactive visualization of information system dynamics using a java-based schematic editor and simulator.
Munshi, A. (2009). The opencl specication. In Hot Chips 21 Symposium (HCS), 2009
OpenCL. OpenclTM zone – Accelerate Your Applications. http://developer.amd.com/tools-and-sdks/opencl-zone/. Accessed: 2017-08-09.
Palumbo, F., Fanni, T., Sau, C., and Meloni, P. (2017). Power-awarness in coarse-grained recongurable multi-functional architectures: a dataow based strategy. Journal of Signal Processing Systems, 87(1):81–106.
Penha, J. C., Fontes, G., and Ferreira, R. (2016). MIPSFPGA Um simulador mips incremental com validação em fpga. International Journal in Computer Architecture Education (IJCAE), 5(1):19–25.
Putnam, A., Cauleld, A. M., Chung, E. S., Chiou, D., Constantinides, K., Demme, J., Esmaeilzadeh, H., Fowers, J., Gopal, G. P., Gray, J., et al. (2014). A recongurable fabric for accelerating large-scale datacenter services. In Computer Architecture (ISCA), 2014 ACM/IEEE 41st International Symposium on, pages 13–24. IEEE.
Stewart, R., Bhowmik, D., Wallace, A., and Michaelson, G. (2017). Prole guided dataow transformation for fpgas and cpus. Journal of Signal Processing Systems, 87(1):3– 20.
Stitt, G. (2011). Are eld-programmable gate arrays ready for the mainstream? IEEE Micro, 31(6):58–63.
Takamaeda-Yamazaki, S. Veriloggen: A library for constructing a verilog hdl source code in python. https://github.com/PyHDI/veriloggen. Accessed: 2017-0720.
Ul-Abdin, Z. and Yang, M. (2017). A radar signal processing case study for dataow programming of manycores. Journal of Signal Processing Systems, 87(1):49–62.
Winans, J. (2015). On dataow computing with openspl.
Xilinx. Xilinx – All Programmable. https://www.xilinx.com/. Accessed: 2017-08-09.
Choi, Y.-k., Cong, J., Fang, Z., Hao, Y., Reinman, G., and Wei, P. (2016). A quantitative analysis on microarchitectures of modern cpu-fpga platforms. In Design Automation Conference (DAC). ACM/EEE.
Ferreira, R., Cardoso, J. M., and Neto, H. C. (2004). An environment for exploring data-driven architectures. In Int. Conference on Field-Programmable Logic and Applications (FPL).
Ferreira, R., Cardoso, J. M., Toledo, A., and Neto, H. C. (2005). Data-driven regular recongurable arrays: design space exploration and mapping. In Int. Conf. on Embedded Computer Systems Architectures, Modeling and Simulation SAMOS.
Ferreira, R., Nacif, J., Magalhaes, S., de Almeida, T., and Pacico, R. (2015). Be a simulator developer and go beyond in computing engineering. In Frontiers in Education Conference (FIE). IEEE.
Gupta, P. (2016). Accelerating datacenter workloads. In 26th International Conference on Field Programmable Logic and Applications.
Gupta, P. K. (2015). Xeon+ fpga platform for the data center. In Fourth Workshop on the Intersections of Computer Architecture and Recongurable Logic, volume 119.
Hendrich, N. (2000). A java-based framework for simulation and teaching: Hades—the hamburg design system. In Microelectronics Education, pages 285–288. Springer.
IntelFPGA. Intel FPGA Acceleratiing The Smart and Connected World. https: //www.altera.com/. Accessed: 2017-08-09.
Kim, E., Kim, K., and In, H. P. (2010). A multi-view api impact analysis for open spl platform. In Advanced Communication Technology (ICACT), 2010 The 12th International Conference on, volume 1, pages 686–691. IEEE.
Ling, A. C., Aydonat, U., O'Connell, S., Capalija, D., and Chiu, G. R. (2017). Creating high performance applications with intel's fpga openclTM sdk. In Proceedings of the 5th International Workshop on OpenCL, page 11. ACM.
Marwedel, P., Cong, K., and Schwenk, S. (2002). Ravi: Interactive visualization of information system dynamics using a java-based schematic editor and simulator.
Munshi, A. (2009). The opencl specication. In Hot Chips 21 Symposium (HCS), 2009
OpenCL. OpenclTM zone – Accelerate Your Applications. http://developer.amd.com/tools-and-sdks/opencl-zone/. Accessed: 2017-08-09.
Palumbo, F., Fanni, T., Sau, C., and Meloni, P. (2017). Power-awarness in coarse-grained recongurable multi-functional architectures: a dataow based strategy. Journal of Signal Processing Systems, 87(1):81–106.
Penha, J. C., Fontes, G., and Ferreira, R. (2016). MIPSFPGA Um simulador mips incremental com validação em fpga. International Journal in Computer Architecture Education (IJCAE), 5(1):19–25.
Putnam, A., Cauleld, A. M., Chung, E. S., Chiou, D., Constantinides, K., Demme, J., Esmaeilzadeh, H., Fowers, J., Gopal, G. P., Gray, J., et al. (2014). A recongurable fabric for accelerating large-scale datacenter services. In Computer Architecture (ISCA), 2014 ACM/IEEE 41st International Symposium on, pages 13–24. IEEE.
Stewart, R., Bhowmik, D., Wallace, A., and Michaelson, G. (2017). Prole guided dataow transformation for fpgas and cpus. Journal of Signal Processing Systems, 87(1):3– 20.
Stitt, G. (2011). Are eld-programmable gate arrays ready for the mainstream? IEEE Micro, 31(6):58–63.
Takamaeda-Yamazaki, S. Veriloggen: A library for constructing a verilog hdl source code in python. https://github.com/PyHDI/veriloggen. Accessed: 2017-0720.
Ul-Abdin, Z. and Yang, M. (2017). A radar signal processing case study for dataow programming of manycores. Journal of Signal Processing Systems, 87(1):49–62.
Winans, J. (2015). On dataow computing with openspl.
Xilinx. Xilinx – All Programmable. https://www.xilinx.com/. Accessed: 2017-08-09.
Publicado
17/10/2017
Como Citar
PENHA, Jeronimo; BRAGANÇA, Lucas; ALMEIDA, Danilo; NACIF, Jose; FERREIRA, Ricardo.
ADD - Uma Ferramenta de Projeto de Aceleradores com DataFlow para Alto Desempenho. In: SIMPÓSIO EM SISTEMAS COMPUTACIONAIS DE ALTO DESEMPENHO (SSCAD), 18. , 2017, Campinas.
Anais [...].
Porto Alegre: Sociedade Brasileira de Computação,
2017
.
p. 4-15.
DOI: https://doi.org/10.5753/wscad.2017.234.
