Análise Arquitetural Comparativa do Desempenho de Redes-em-Chip Baseada em Simulação
Resumo
As Redes-em-Chip são a infraestrutura de comunicação adotada nos sistemas many-core atuais e diversos estudos têm comparado o desempenho de arquiteturas de rede. Porém, esses trabalhos carecem de análises quantitativas ou de abrangência arquitetural. Para superar essas limitações, este artigo apresenta uma biblioteca de componentes de simulação que possibilita a modelagem de diferentes alternativas arquiteturais e a coleta de dados para uma comparação quantitativa. Um amplo conjunto de experimentos foi realizado para demonstrar a efetividade da biblioteca implementada. Os resultados obtidos permitem identificar as melhores alternativas de rede para diferentes cenários de tráfego.
Referências
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Andriahantenaina, A., Charlery, H., Greiner, A., Mortiez, L., Zeferino, C. A. (2003) "SPIN: a scalable, packet switched on-chip micro-network", In Design Automation and Test on Europe, IEEE CS, Los Alamitos, p. 70-73.
Dally, W., Towles, B. (2004). Principles and Practices of Interconnection Networks. San Francisco: Morgan Kaufmann.
Du, G., He, J., Song, Y., Zhang, D., Wu, H. (2013). "Comparison of NoC routing algorithms based on packet-circuit switching". In 3rd Int. Conf. on Information Science and Technology, IEEE, Yangzhou, p. 707-710.
Ghidini, Y., Weber, T., Moreno, E., Quadros, I., Fagundes, R., Marcon, C. (2012). "Topological impact on latency and throughput: 2D versus 3D NoC comparison". In 25th Symp. on Integrated Circuits and Systems Design, IEEE, Brasília, p 1-6.
Hao, P., Qii, H., Jiaqin, D., Pan, P. (2011). "Comparison of 2D MESH routing algorithm in NOC". In 9th Int. Conf. on ASIC, IEEE, Xiamen, p. 791-795.
Harbin, J., Indrusiak, L. S. (2016). "Comparative performance evaluation of latency and link dynamic power consumption modelling algorithms in wormhole switching networks on chip". Journal of Systems Architecture, New York, v. 63, p. 33-47.
Jaina, A., Kumarb, A., Sharmac, S. (2015). "Comparative Design and Analysis of Mesh, Torus and Ring NoC". In Int. Conf. on Computer, Communication and Convergence, Procedia Computer Science, v. 48, p. 330-337.
Jetly, Krunal (2013). Experimental Comparison of Store-and-Forward and Wormhole NoC Routers for FPGA's. MSc Thesis, Dept. Electrical and Computer Enginnering University of Windsor, Windsor.
Ju, X., Yang, L. (2012). "Performance analysis and comparison of 2 × 4 Network on Chip topology". Journal of Microprocessors and Microsystems, New York, v. 36, n. 6, p. 505-509.
Kalimuthu, A., Karthikeyan, M. (2012). "Comparative performance evaluation of power and area Network on Chip (NoC) architectures". In Int. Conf. on Computing Intelligence and Computing Research, IEEE, Coimbatore, p. 1-4.
Manna. K., Chattopadhaya, S., Sengupta, I (2012). "An efficient routing technique for mesh-oftree-based NoC and its performance comparison". Int. Journal of High Performance Systems Architecture, Geneva, v. 4, n. 1, p. 25-37.
Ogras, U. Y., Marculescu, R. (2013). Modeling, Analysis and Optimization of Network-on-Chip Communication Architectures, Springer, v. 184.
Pandey, D., Gupta, K. (2012). "Comparison between Mesh and Custom Topologies of Network-on-Chip Architectures". Int. Journal of Scientific Engineering and Technology, Gulmohar, v. 1, n. 5, p. 243-247.
Parandkar, P., Dalal, J. K., Katiyal, S. (2012). "Performance Comparison of XY, OE and DY Ad Routing Algorithm by Load Variation Analysis of 2-Dimensional Mesh Topology Based Network-on-Chip". BVICAM Int. Journal of Information Technology, New Delhi, v. 4, n. 1, p. 391-396.
Radfar, F., Zabihi, M., Sarvari, R. (2014). "Comparison between optimal interconnection network in different 2D and 3D NoC structures". In 27th Int. System-On-Chip Conf., IEEE, Las Vegas, p. 171-176.
Romanov, O., Lysenko, O. (2012). "The comparative analysis of the efficiency of regular and pseudo-optimal topologies of Networks-on-Chip based on Netmaker". In Mediterranean Conf. on Embedded Computing, IEEE, Bar, p. 13-16.
Sadawarte, Y. A., Gaikwad, M. A., Patrikar, R. M. (2011). "Comparative study of switching techniques for network-on-chip architecture". In: Int. Conf. on Communication, Computing and Security, ACM, New York, p. 243-246.
Silva, E. A. (2014). RedScarf: ambiente para avaliação de desempenho de Rede-em-Chip. BSCS Work, Universidade do Vale do Itajaí, Itajaí.
Silva, E. A. (2017). Análise Comparativa do Desempenho de Arquiteturas de Redes-em-Chip baseada em Simulação. M.Sc. Thesis, Universidade do Vale do Itajaí, Itajaí
Sllame, A. M., Abdelkader, A. H. (2014). "A comparative study between fat tree and mesh network-on-chip interconnection architectures". In 14th Middle Eastern Simulation and Modeling Multiconference, Eurosis, Muscat, p. 31-37.
Tedesco, L., Mello, A., Garibotti, D., Calazans, N., Moraes, F. (2005). "Traffic generation and performance evaluation for mesh-based NoCs". In 18th Symp. On Integrated Circuits and Systems Design. Florianópolis, p. 184-189.
The Qt Company (2017), "Qt", https://qt.io, August.
Wang, P., Ma, S., Lu, H., Wang, Z. (2014). "A comprehensive comparison between virtual cutthrough and wormhole routers for cache coherent network on-chips". Journal IEICE Electronic Express, Tokyo, v. 11, n. 14, p. 1-12.
Yin, A., Chen, N., Liljeberg, P., Tenhunen, H. (2012). "Comparison of mesh and honeycomb network-on-chip architectures". In Conf. on Industrial Electronics and Applications, IEEE, Singapura, p. 1716-1720.
Andriahantenaina, A., Charlery, H., Greiner, A., Mortiez, L., Zeferino, C. A. (2003) "SPIN: a scalable, packet switched on-chip micro-network", In Design Automation and Test on Europe, IEEE CS, Los Alamitos, p. 70-73.
Dally, W., Towles, B. (2004). Principles and Practices of Interconnection Networks. San Francisco: Morgan Kaufmann.
Du, G., He, J., Song, Y., Zhang, D., Wu, H. (2013). "Comparison of NoC routing algorithms based on packet-circuit switching". In 3rd Int. Conf. on Information Science and Technology, IEEE, Yangzhou, p. 707-710.
Ghidini, Y., Weber, T., Moreno, E., Quadros, I., Fagundes, R., Marcon, C. (2012). "Topological impact on latency and throughput: 2D versus 3D NoC comparison". In 25th Symp. on Integrated Circuits and Systems Design, IEEE, Brasília, p 1-6.
Hao, P., Qii, H., Jiaqin, D., Pan, P. (2011). "Comparison of 2D MESH routing algorithm in NOC". In 9th Int. Conf. on ASIC, IEEE, Xiamen, p. 791-795.
Harbin, J., Indrusiak, L. S. (2016). "Comparative performance evaluation of latency and link dynamic power consumption modelling algorithms in wormhole switching networks on chip". Journal of Systems Architecture, New York, v. 63, p. 33-47.
Jaina, A., Kumarb, A., Sharmac, S. (2015). "Comparative Design and Analysis of Mesh, Torus and Ring NoC". In Int. Conf. on Computer, Communication and Convergence, Procedia Computer Science, v. 48, p. 330-337.
Jetly, Krunal (2013). Experimental Comparison of Store-and-Forward and Wormhole NoC Routers for FPGA's. MSc Thesis, Dept. Electrical and Computer Enginnering University of Windsor, Windsor.
Ju, X., Yang, L. (2012). "Performance analysis and comparison of 2 × 4 Network on Chip topology". Journal of Microprocessors and Microsystems, New York, v. 36, n. 6, p. 505-509.
Kalimuthu, A., Karthikeyan, M. (2012). "Comparative performance evaluation of power and area Network on Chip (NoC) architectures". In Int. Conf. on Computing Intelligence and Computing Research, IEEE, Coimbatore, p. 1-4.
Manna. K., Chattopadhaya, S., Sengupta, I (2012). "An efficient routing technique for mesh-oftree-based NoC and its performance comparison". Int. Journal of High Performance Systems Architecture, Geneva, v. 4, n. 1, p. 25-37.
Ogras, U. Y., Marculescu, R. (2013). Modeling, Analysis and Optimization of Network-on-Chip Communication Architectures, Springer, v. 184.
Pandey, D., Gupta, K. (2012). "Comparison between Mesh and Custom Topologies of Network-on-Chip Architectures". Int. Journal of Scientific Engineering and Technology, Gulmohar, v. 1, n. 5, p. 243-247.
Parandkar, P., Dalal, J. K., Katiyal, S. (2012). "Performance Comparison of XY, OE and DY Ad Routing Algorithm by Load Variation Analysis of 2-Dimensional Mesh Topology Based Network-on-Chip". BVICAM Int. Journal of Information Technology, New Delhi, v. 4, n. 1, p. 391-396.
Radfar, F., Zabihi, M., Sarvari, R. (2014). "Comparison between optimal interconnection network in different 2D and 3D NoC structures". In 27th Int. System-On-Chip Conf., IEEE, Las Vegas, p. 171-176.
Romanov, O., Lysenko, O. (2012). "The comparative analysis of the efficiency of regular and pseudo-optimal topologies of Networks-on-Chip based on Netmaker". In Mediterranean Conf. on Embedded Computing, IEEE, Bar, p. 13-16.
Sadawarte, Y. A., Gaikwad, M. A., Patrikar, R. M. (2011). "Comparative study of switching techniques for network-on-chip architecture". In: Int. Conf. on Communication, Computing and Security, ACM, New York, p. 243-246.
Silva, E. A. (2014). RedScarf: ambiente para avaliação de desempenho de Rede-em-Chip. BSCS Work, Universidade do Vale do Itajaí, Itajaí.
Silva, E. A. (2017). Análise Comparativa do Desempenho de Arquiteturas de Redes-em-Chip baseada em Simulação. M.Sc. Thesis, Universidade do Vale do Itajaí, Itajaí
Sllame, A. M., Abdelkader, A. H. (2014). "A comparative study between fat tree and mesh network-on-chip interconnection architectures". In 14th Middle Eastern Simulation and Modeling Multiconference, Eurosis, Muscat, p. 31-37.
Tedesco, L., Mello, A., Garibotti, D., Calazans, N., Moraes, F. (2005). "Traffic generation and performance evaluation for mesh-based NoCs". In 18th Symp. On Integrated Circuits and Systems Design. Florianópolis, p. 184-189.
The Qt Company (2017), "Qt", https://qt.io, August.
Wang, P., Ma, S., Lu, H., Wang, Z. (2014). "A comprehensive comparison between virtual cutthrough and wormhole routers for cache coherent network on-chips". Journal IEICE Electronic Express, Tokyo, v. 11, n. 14, p. 1-12.
Yin, A., Chen, N., Liljeberg, P., Tenhunen, H. (2012). "Comparison of mesh and honeycomb network-on-chip architectures". In Conf. on Industrial Electronics and Applications, IEEE, Singapura, p. 1716-1720.
Publicado
17/10/2017
Como Citar
ALVES DA SILVA, Eduardo; ALBENES ZEFERINO, Cesar.
Análise Arquitetural Comparativa do Desempenho de Redes-em-Chip Baseada em Simulação. In: SIMPÓSIO EM SISTEMAS COMPUTACIONAIS DE ALTO DESEMPENHO (SSCAD), 18. , 2017, Campinas.
Anais [...].
Porto Alegre: Sociedade Brasileira de Computação,
2017
.
p. 268-279.
DOI: https://doi.org/10.5753/wscad.2017.255.
