Exploração Eficiente em Espaços de Projeto de Comunicação em Plataformas Multiprocessadoras Baseadas em Barramentos
Abstract
Embedded systems have became very complex due to the new applications requirements, thereby needing more than one processor, different types of memory and peripherals. To make more efficient the communication among these devices, the designer must customize the onchip communication structure. When using buses for the communication, many parameters must be considered, since they can directly impact on the performance of the entire system. This paper presents a new approach that, compared to traditional simulation approaches, aims to increase the performance of the exploration task of the bus configuration options included in the design space.
References
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Pasricha, S.; Dutt, N.; Bozorgzadeh, E. and BenRomdhane, M. (2004) “Floorplanaware Bus Architecture Synthesis”, CECS Technical Report 0427.
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Shin, C.; Kim, Y.T.; Chung, E.Y.; Choi, K.M.; Kong, J.T. and Eo, S.K. (2004) “Fast Exploration of Parameterized Bus Architecture for CommunicationCentric SoC design”, Proc. of the conference on Design, automation and test in Europe.
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ARM AMBA. (1999) “AMBA Specification rev. 2.0”, http://wwwmicro. deis.unibo.it/~magagni/amba99.pdf, May.
Bouajila, A.; Zeppenfeld, J.; Stechele, W.; Bernauer, A.; Bringmann, O.; Rosenstiel, W. and Herkersdorf, A. (2011) “Autonomic System on Chip Platform”, Organic Computing A Paradigm Shift for Complex Systems. Springer.
Cho, Y.S. ; Choi, E.J. and Cho, K.R. (2006) “Modeling and analysis of the system bus latency on the SoC platform”, Proceedings of the International Workshop on SystemLevel Interconnect Prediction, pages 67–74.
Cormen, T.H., Leiserson, C.E. Rivest, R.L. and Stein, C. (2009) “Introduction to Algorithms, 3rd. Ed.”, The Mit Press.
Gasteier, M. and Glesner, M. (1999) “Busbased communication synthesis on system level”, ACM Trans. Design Automation Electronic Systems, pages 1–11.
Jerraya, A. A.; Wolf, W. (2004) “Multiprocessor systemsonchips”, Morgan Kaufmann.
Joo, Y.P.; Kim, S. and Ha, S. (2009) “Onchip communication architecture exploration for processorpoolbased MPSoC”, Proc. of Design, Automation and Test in Europe.
Kim, S.; Im, C. and Ha, S. (2003) “Scheduleaware Performance Estimation of Communication Architecture for Efficient Design Space Exploration”, Proc. of the Intl. Conf. onHardware/Software Codesign and System Synthesis, pages 195–200.
Lahiri, K. and Raghunathan, A. (2004) “Power Analysis of Systemlevel Onchip Communication Architectures”, Proc. of the Conference on Hardware/Software Codesignand System Synthesis, pages 236–241.
Lahiri, K., Raghunathan, A., Dey, S. (2001) “SystemLevel Performance Analysis for Designing OnChip Communication Architectures”, IEEE Trans. on ComputerAided Design of Integrated Circuits and Systems, vol. 20, no.6, pp.768783.
Lukasiewycz, M.; Streubühr, M.; Glaß, M.; Haubelt, C. and Teich, J. (2009) “Combined System Synthesis and Communication Architecture Exploration for MPSoCs”, Proceedings of Design, Automation and Test in Europe, pp. 472477.
Pasricha, S.; Dutt, N.; Bozorgzadeh, E. and BenRomdhane, M. (2004) “Floorplanaware Bus Architecture Synthesis”, CECS Technical Report 0427.
Pasricha, S.; Dutt, N.; BenRomdhane, M. (2005) “Using TLM for Exploring Busbased SoC Communication Architectures”, Int. Conference on Applicationspecific Systems, Architectures and Processors, Samos, Greece.
Rowson, J. A. and SangiovanniVincentelli. A. (1997) “Interface based design”, Proceedings of the Design Automation Conference, pages 178–183.
Shanti, D. and Amutha, R. (2012) “Simulation of Inter Processor Communication Architecture in MPSoC”, European J. of Scientific Research, Vol.72 No.1, pp. 7483.
Shin, C.; Kim, Y.T.; Chung, E.Y.; Choi, K.M.; Kong, J.T. and Eo, S.K. (2004) “Fast Exploration of Parameterized Bus Architecture for CommunicationCentric SoC design”, Proc. of the conference on Design, automation and test in Europe.
Wild, T.; Hekerdof, A.. Ohlendorf, R. (2006) “Performance evaluation for system onchip architectures using tracebased transaction level simulation”, Proceedings of the conference on Design, automation and test in Europe, pages 248–253.
Woo, S. C., Ohara, M., Torrie, E., Singh, J. P. and Gupta, A. (1995) “The SPLASH2 Programs: Characterization and Methodological Considerations”, Proc. of the 22nd International Symposium on Computer Architecture, pages 2436, Ligure, Italy.
Published
2015-07-20
How to Cite
ESMERALDO, Guilherme; BARROS, Edna.
Exploração Eficiente em Espaços de Projeto de Comunicação em Plataformas Multiprocessadoras Baseadas em Barramentos. In: WORKSHOP ON PERFORMANCE OF COMPUTER AND COMMUNICATION SYSTEMS (WPERFORMANCE), 14. , 2015, Recife.
Anais [...].
Porto Alegre: Sociedade Brasileira de Computação,
2015
.
p. 134-147.
ISSN 2595-6167.
DOI: https://doi.org/10.5753/wperformance.2015.10403.
