Avaliação de um Modelo de Consumo Energético Aplicado ao Mapeamento de Processos
Resumo
A redução do consumo energético é hoje um dos grandes desafios da computação, essencial para viabilizar as novas gerações de computadores e arquiteturas paralelas de grande escala. Nesse contexto, é fundamental o entendimento de onde e como a energia é aplicada, e quais técnicas podem ser empregadas para aumentar sua eficiência. A modelagem do consumo de energia visa facilitar esta análise, porém sua precisão com relação a arquiteturas reais ainda é pouco explorada. Sendo assim, este artigo visa estudar um modelo de consumo energético para arquiteturas com hierarquia de cache, de forma a aplicá-lo no contexto de mapeamento de processo em uma arquitetura real.Referências
Alves, M. A. Z., Freitas, H. C., and Navaux, P. O. A. (2009). Investigation of shared l2 cache on many-core processors. In Proceedings Workshop on Many-Core, pages 21–30, Berlin. VDE Verlag GMBH.
Bellosa, F. (2000). The benefits of event: driven energy accounting in power-sensitive systems. In Proceedings of the 9th workshop on ACM SIGOPS European workshop: beyond the PC: new challenges for the operating system, pages 37–42. ACM.
Bircher, W., Valluri, M., Law, J., and John, L. (2005). Runtime identification of microprocessor energy saving opportunities. In Proceedings of the 2005 international symposium on Low power electronics and design, pages 275–280. ACM.
Cruz, E. H., Alves, M. A., and Navaux, P. O. (2010). Process mapping based on memory access traces. In Computing Systems (WSCAD-SCC), 2010 11th Symposium on, pages 72 –79.
Cruz, E. H., Ribeiro, C. P., Alves, M. A., Carissimi, A., Mehaut, J., and Navaux, P. O. (2011a). Using memory access traces to map threads and data on hierarchical multicore platforms. In 25th IPDPS 13th Workshop on Advances in Parallel and Distributed Computational Models.
Cruz, E. H. M., Padoin, E. L., Boito, F. Z., and Navaux, P. O. A. (2011b). Avaliando consumo de energia no mapeamento de processos. In XI Escola Regional de Alto Desempenho (ERAD 2011), volume IX, pages 93–94. SBC.
Donofrio, D., Oliker, L., Shalf, J., Wehner, M. F., Rowen, C., Krueger, J., Kamil, S., and Mohiyuddin, M. (2009). Energy-efficient computing for extreme-scale science. Computer, 42:62–71.
Gordon-Ross, A., Vahid, F., and Dutt, N. (2005). Fast configurable-cache tuning with a unified second-level cache. In Proceedings of the 2005 international symposium on Low power electronics and design, pages 323–326. ACM.
Hennessy, J. L. and Patterson, D. A. (2007). Computer Architecture: A Quantitative Approach. Elsevier, USA, 4th edition.
Herranz, A. and Moreno-Navarro, J. (2003). Cache Configuration Exploration on Prototyping Platforms. In Proceedings of the 14th IEEE International Workshop on Rapid System Prototyping (RSP’03), page 164. IEEE Computer Society.
Hicks, P., Walnock, M., and Owens, R. (1997). Analysis of power consumption in memory hierarchies. In Proceedings of the 1997 international symposium on Low power electronics and design, pages 239–242. ACM.
Hsu, C.-h. and Feng, W.-c. (2005). A power-aware run-time system for high-performance computing. In Proceedings of the 2005 ACM/IEEE conference on Supercomputing, SC ’05, pages 1–, Washington, DC, USA. IEEE Computer Society.
Jin, H., Frumkin, M., and Yan, J. (1999). The openmp implementation of nas parallel benchmarks and its performance. In Technical Report: NAS-99-011.
Kim, H. S., Narayanan, V., Kandemir, M., and Irwin, M. J. (2000). Multiple access caches: Energy implications. In Proceedings of the IEEE Computer Society Annual Workshop on VLSI (WVLSI’00), WVLSI ’00, pages 53–, Washington, DC, USA. IEEE Computer Society.
Kogge, P., Bergman, K., Borkar, S., Campbell, D., Carson, W., Dally, W., Denneau, M., Franzon, P., Harrod, W., Hill, K., and Others (2008). Exascale computing study: Technology challenges in achieving exascale systems. Technical report, University of Notre Dame, CSE Dept.
Kumar, R., Zyuban, V., and Tullsen, D. M. (2005). Interconnections in multi-core architectures: Understanding mechanisms, overheads and scaling. In Proceedings of the 32nd annual international symposium on Computer Architecture, ISCA ’05, pages 408–419, Washington, DC, USA. IEEE Computer Society.
Shiue, W. and Chakrabarti, C. (1999). Memory exploration for low power, embedded systems.
Silva-Filho, A., Cordeiro, F., Sant Anna, R., and Lima, M. (2006). Heuristic for two-level cache hierarchy exploration considering energy consumption and performance. Lecture notes in computer science, 4148:75.
Tam, D., Azimi, R., and Stumm, M. (2007). Thread clustering: sharing-aware scheduling on smp-cmp-smt multiprocessors. SIGOPS Oper. Syst. Rev., 41(3):47–58.
Zarandi, H. and Miremadi, S. (2005). Hierarchical multiple associative mapping in cache memories.
Zhang, C. and Vahid, F. (2003). Cache configuration exploration on prototyping platforms.
Bellosa, F. (2000). The benefits of event: driven energy accounting in power-sensitive systems. In Proceedings of the 9th workshop on ACM SIGOPS European workshop: beyond the PC: new challenges for the operating system, pages 37–42. ACM.
Bircher, W., Valluri, M., Law, J., and John, L. (2005). Runtime identification of microprocessor energy saving opportunities. In Proceedings of the 2005 international symposium on Low power electronics and design, pages 275–280. ACM.
Cruz, E. H., Alves, M. A., and Navaux, P. O. (2010). Process mapping based on memory access traces. In Computing Systems (WSCAD-SCC), 2010 11th Symposium on, pages 72 –79.
Cruz, E. H., Ribeiro, C. P., Alves, M. A., Carissimi, A., Mehaut, J., and Navaux, P. O. (2011a). Using memory access traces to map threads and data on hierarchical multicore platforms. In 25th IPDPS 13th Workshop on Advances in Parallel and Distributed Computational Models.
Cruz, E. H. M., Padoin, E. L., Boito, F. Z., and Navaux, P. O. A. (2011b). Avaliando consumo de energia no mapeamento de processos. In XI Escola Regional de Alto Desempenho (ERAD 2011), volume IX, pages 93–94. SBC.
Donofrio, D., Oliker, L., Shalf, J., Wehner, M. F., Rowen, C., Krueger, J., Kamil, S., and Mohiyuddin, M. (2009). Energy-efficient computing for extreme-scale science. Computer, 42:62–71.
Gordon-Ross, A., Vahid, F., and Dutt, N. (2005). Fast configurable-cache tuning with a unified second-level cache. In Proceedings of the 2005 international symposium on Low power electronics and design, pages 323–326. ACM.
Hennessy, J. L. and Patterson, D. A. (2007). Computer Architecture: A Quantitative Approach. Elsevier, USA, 4th edition.
Herranz, A. and Moreno-Navarro, J. (2003). Cache Configuration Exploration on Prototyping Platforms. In Proceedings of the 14th IEEE International Workshop on Rapid System Prototyping (RSP’03), page 164. IEEE Computer Society.
Hicks, P., Walnock, M., and Owens, R. (1997). Analysis of power consumption in memory hierarchies. In Proceedings of the 1997 international symposium on Low power electronics and design, pages 239–242. ACM.
Hsu, C.-h. and Feng, W.-c. (2005). A power-aware run-time system for high-performance computing. In Proceedings of the 2005 ACM/IEEE conference on Supercomputing, SC ’05, pages 1–, Washington, DC, USA. IEEE Computer Society.
Jin, H., Frumkin, M., and Yan, J. (1999). The openmp implementation of nas parallel benchmarks and its performance. In Technical Report: NAS-99-011.
Kim, H. S., Narayanan, V., Kandemir, M., and Irwin, M. J. (2000). Multiple access caches: Energy implications. In Proceedings of the IEEE Computer Society Annual Workshop on VLSI (WVLSI’00), WVLSI ’00, pages 53–, Washington, DC, USA. IEEE Computer Society.
Kogge, P., Bergman, K., Borkar, S., Campbell, D., Carson, W., Dally, W., Denneau, M., Franzon, P., Harrod, W., Hill, K., and Others (2008). Exascale computing study: Technology challenges in achieving exascale systems. Technical report, University of Notre Dame, CSE Dept.
Kumar, R., Zyuban, V., and Tullsen, D. M. (2005). Interconnections in multi-core architectures: Understanding mechanisms, overheads and scaling. In Proceedings of the 32nd annual international symposium on Computer Architecture, ISCA ’05, pages 408–419, Washington, DC, USA. IEEE Computer Society.
Shiue, W. and Chakrabarti, C. (1999). Memory exploration for low power, embedded systems.
Silva-Filho, A., Cordeiro, F., Sant Anna, R., and Lima, M. (2006). Heuristic for two-level cache hierarchy exploration considering energy consumption and performance. Lecture notes in computer science, 4148:75.
Tam, D., Azimi, R., and Stumm, M. (2007). Thread clustering: sharing-aware scheduling on smp-cmp-smt multiprocessors. SIGOPS Oper. Syst. Rev., 41(3):47–58.
Zarandi, H. and Miremadi, S. (2005). Hierarchical multiple associative mapping in cache memories.
Zhang, C. and Vahid, F. (2003). Cache configuration exploration on prototyping platforms.
Publicado
19/07/2011
Como Citar
PADOIN, Edson L.; CRUZ, Eduardo H. M.; BOITO, Francieli Z.; MOREIRA, Francis B.; PILLA, Laércio L.; KASSICK, Rodrigo V.; NAVAUX, Philippe O. A..
Avaliação de um Modelo de Consumo Energético Aplicado ao Mapeamento de Processos. In: WORKSHOP EM DESEMPENHO DE SISTEMAS COMPUTACIONAIS E DE COMUNICAÇÃO (WPERFORMANCE), 10. , 2011, Natal/RN.
Anais [...].
Porto Alegre: Sociedade Brasileira de Computação,
2011
.
p. 2075-2087.
ISSN 2595-6167.
