Impacto de falhas transientes em memórias SRAM em nanotecnologia
Resumo
Esse trabalho avalia o impacto de falhas transientes induzidos por radiação em cinco topologias de células SRAM: 6T, 8T, 9T, 8T-SER e DICE. A análise explora as características temporais, de dissipação de potência e o limiar de LET durante a operação de armazenamento. As células de memória foram descritas utilizando o modelo preditivo na tecnologia de 16nm. Os resultados mostram o melhor desempenho da célula DICE como a opção mais robusta quanto aos efeitos de radiação. A célula 8T-SER obteve a melhor estabilidade considerando a tolerância ao ruído. Também são apresentados os ganhos na utilização da célula 8T em relação a 6T quando consideradas as métricas de atraso e consumo energético.
Palavras-chave:
SRAM, Soft Errors, Single Event upset, SNM, CMOS
Referências
Almeida, R. B., Marques, C. M., Butzen, P. F., Silva, F. R. G., Reis, R. A., & Meinhardt, C. (2018). Analysis of 6 T SRAM cell in sub-45 nm CMOS and FinFET technologies. Microelectronics Reliability, 88, 196-202.
Baumann, R. C. (2005). Radiation-induced soft errors in advanced semiconductor technologies. IEEE Transactions on Device and materials reliability, 5(3), 305-316.
Cao, X., Xiao, L., Li, L., Li, J., & Wang, T. (2019). Simulation of Proton Induced Single Event Upsets in Bulk Nano-CMOS SRAMs. In 2019 Int. Conf. on IC Design and Tech (ICICDT) (pp. 1-4). IEEE.
Feki, A., Allard, B., Turgis, D., Lafont, J. C., & Ciampolini, L. (2012, November). Proposal of a new ultra low leakage 10T sub threshold SRAM bitcell. In 2012 Int. SoC Design Conf. (ISOCC) (pp. 470-474). IEEE.
Gill, B., Seifert, N., & Zia, V. (2019) Comparison of alpha-particle and neutron-induced combinational and sequential logic error rates at the 32nm technology node. In 2009 IEEE Int. Reliability Physics Symp. (pp. 199-205). IEEE.
Kim, T. T. H., Lee, Z. C., & Do, A. T. (2018). A 32 kb 9T near-threshold SRAM with enhanced read ability at ultra-low voltage operation. Solid-State Elect., 139, 60-68.
Manabe, S., Watanabe, Y., Liao, W., Hashimoto, M., & Abe, S. I. (2019). Estimation of muon-induced SEU rates for 65-nm bulk and UTBB-SOI SRAMs. IEEE Transactions on Nuclear Science, 66(7), 1398-1403.
Marques, C.M., Longo, C.A.S. N. S., Almeida, R. B., Meinhardt, C., Butzen, P.F. (2018a). Impacto de falhas Stuck-Open e Stuck-on em células de memória 6T SRAM de 16nm. In 24th Iberchip workshop.
Marques, C.M., Almeida, R. B., Meinhardt, C., Butzen, P.F. (2018b). Analyze of permanent and transient faults in 6T SRAM cell. Simpósio Sul de Microeletrônica.
Marques, C.M., Almeida, R. B., Meinhardt, C., Butzen, P.F. (2018c). Comparing the SEU robustness of 6T and 8T-SER SRAM cells at 16nm. In Chip in the Pampa 2018 – 18th Microelectronics Students Forum (SFORUM 2018).
Marques, C.M., Almeida, R. B., Meinhardt, C., Butzen, P.F. (2019a). Analyze and Comparison of 6T and 8T-SER SRAM topologies in 16nm CMOS technology. In 34th Simpósio Sul de Microeletrônica.
Marques, C.M., Almeida, R. B., Meinhardt, C., Butzen, P.F. (2019b). A comparative evaluation of SRAM topologies. In Chip in the Sampa 2019 – 19th Microelectronics Students Forum (SFORUM 2019).
Marques, C.M., Almeida, R. B., Meinhardt, C., Butzen, P.F. (2019c). Avaliação dos efeitos de falhas do tipo single event upset sobre células de memória SRAM na tecnologia de 16nm. In 8th Conferência Sul em modelagem computacional.
Marques, C.M., Meinhardt, C., Butzen, P.F. (2020a). Avaliação dos efeitos de radiação em células SRAM. In 11th Computer on the beach.
Marques, C.M., Butzen, P.F., Meinhardt, C. (2020b). Soft Error Reliability of SRAM Cells during the three operation states. In IEEE Latin American Test Symposium (LATS2020).
Pavlov, A., & Sachdev, M. (2008). CMOS SRAM circuit design and parametric test in nano-scaled technologies: process-aware SRAM design and test (Vol. 40). Springer Science & Business Media.
Rajput, A. S., Pattanaik, M., & Tiwari, R. (2018). Estimation of static noise margin by butterfly method using curve-fitting technique. Journal of Active and Passive Electronic Devices, 13(1), 1-9.
Sandeep, R., Deshpande, N. T., & Aswatha, A. R. (2009). Design and analysis of a new loadless 4T SRAM cell in deep submicron CMOS technologies. In 2009 Second International Conference on Emerging Trends in Engineering & Technology (pp. 155-161). IEEE.
Shah, J. S., Nairn, D., & Sachdev, M. (2015). A 32 kb macro with 8T soft error robust, SRAM cell in 65-nm CMOS. IEEE Transactions on Nuclear Science, 62(3), 1367-1374.
Sharif, K. F., Islam, R., & Biswas, S. N. (2018). A New Model of High Speed 7T SRAM Cell. In 2018 Int. Conf. on Computer, Communication, Chemical, Material and Electronic Engineering (IC4ME2) (pp. 1-4). IEEE.
Singh, J., Mohanty, S. P., & Pradhan, D. K. (2012). Robust SRAM designs and analysis. Springer Science & Business Media.
Stallings, W. (2003). Computer organization and architecture: designing for performance. Pearson Education India.
Baumann, R. C. (2005). Radiation-induced soft errors in advanced semiconductor technologies. IEEE Transactions on Device and materials reliability, 5(3), 305-316.
Cao, X., Xiao, L., Li, L., Li, J., & Wang, T. (2019). Simulation of Proton Induced Single Event Upsets in Bulk Nano-CMOS SRAMs. In 2019 Int. Conf. on IC Design and Tech (ICICDT) (pp. 1-4). IEEE.
Feki, A., Allard, B., Turgis, D., Lafont, J. C., & Ciampolini, L. (2012, November). Proposal of a new ultra low leakage 10T sub threshold SRAM bitcell. In 2012 Int. SoC Design Conf. (ISOCC) (pp. 470-474). IEEE.
Gill, B., Seifert, N., & Zia, V. (2019) Comparison of alpha-particle and neutron-induced combinational and sequential logic error rates at the 32nm technology node. In 2009 IEEE Int. Reliability Physics Symp. (pp. 199-205). IEEE.
Kim, T. T. H., Lee, Z. C., & Do, A. T. (2018). A 32 kb 9T near-threshold SRAM with enhanced read ability at ultra-low voltage operation. Solid-State Elect., 139, 60-68.
Manabe, S., Watanabe, Y., Liao, W., Hashimoto, M., & Abe, S. I. (2019). Estimation of muon-induced SEU rates for 65-nm bulk and UTBB-SOI SRAMs. IEEE Transactions on Nuclear Science, 66(7), 1398-1403.
Marques, C.M., Longo, C.A.S. N. S., Almeida, R. B., Meinhardt, C., Butzen, P.F. (2018a). Impacto de falhas Stuck-Open e Stuck-on em células de memória 6T SRAM de 16nm. In 24th Iberchip workshop.
Marques, C.M., Almeida, R. B., Meinhardt, C., Butzen, P.F. (2018b). Analyze of permanent and transient faults in 6T SRAM cell. Simpósio Sul de Microeletrônica.
Marques, C.M., Almeida, R. B., Meinhardt, C., Butzen, P.F. (2018c). Comparing the SEU robustness of 6T and 8T-SER SRAM cells at 16nm. In Chip in the Pampa 2018 – 18th Microelectronics Students Forum (SFORUM 2018).
Marques, C.M., Almeida, R. B., Meinhardt, C., Butzen, P.F. (2019a). Analyze and Comparison of 6T and 8T-SER SRAM topologies in 16nm CMOS technology. In 34th Simpósio Sul de Microeletrônica.
Marques, C.M., Almeida, R. B., Meinhardt, C., Butzen, P.F. (2019b). A comparative evaluation of SRAM topologies. In Chip in the Sampa 2019 – 19th Microelectronics Students Forum (SFORUM 2019).
Marques, C.M., Almeida, R. B., Meinhardt, C., Butzen, P.F. (2019c). Avaliação dos efeitos de falhas do tipo single event upset sobre células de memória SRAM na tecnologia de 16nm. In 8th Conferência Sul em modelagem computacional.
Marques, C.M., Meinhardt, C., Butzen, P.F. (2020a). Avaliação dos efeitos de radiação em células SRAM. In 11th Computer on the beach.
Marques, C.M., Butzen, P.F., Meinhardt, C. (2020b). Soft Error Reliability of SRAM Cells during the three operation states. In IEEE Latin American Test Symposium (LATS2020).
Pavlov, A., & Sachdev, M. (2008). CMOS SRAM circuit design and parametric test in nano-scaled technologies: process-aware SRAM design and test (Vol. 40). Springer Science & Business Media.
Rajput, A. S., Pattanaik, M., & Tiwari, R. (2018). Estimation of static noise margin by butterfly method using curve-fitting technique. Journal of Active and Passive Electronic Devices, 13(1), 1-9.
Sandeep, R., Deshpande, N. T., & Aswatha, A. R. (2009). Design and analysis of a new loadless 4T SRAM cell in deep submicron CMOS technologies. In 2009 Second International Conference on Emerging Trends in Engineering & Technology (pp. 155-161). IEEE.
Shah, J. S., Nairn, D., & Sachdev, M. (2015). A 32 kb macro with 8T soft error robust, SRAM cell in 65-nm CMOS. IEEE Transactions on Nuclear Science, 62(3), 1367-1374.
Sharif, K. F., Islam, R., & Biswas, S. N. (2018). A New Model of High Speed 7T SRAM Cell. In 2018 Int. Conf. on Computer, Communication, Chemical, Material and Electronic Engineering (IC4ME2) (pp. 1-4). IEEE.
Singh, J., Mohanty, S. P., & Pradhan, D. K. (2012). Robust SRAM designs and analysis. Springer Science & Business Media.
Stallings, W. (2003). Computer organization and architecture: designing for performance. Pearson Education India.
Publicado
30/06/2020
Como Citar
MARQUES, Cleiton M.; MEINHARDT, Cristina ; BUTZEN, Paulo F..
Impacto de falhas transientes em memórias SRAM em nanotecnologia. In: CONCURSO DE TRABALHOS DE INICIAÇÃO CIENTÍFICA DA SBC (CTIC-SBC), 39. , 2020, Cuiabá.
Anais [...].
Porto Alegre: Sociedade Brasileira de Computação,
2020
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p. 81-90.
